Artificial Neural Network-Based 4-D Hyper-Chaotic System on Field Programmable Gate Array
AbstractIn this presented study, a 4-D hyper-chaotic system newly proposed to the literature, has been implemented as Multi-Layer Feed-Forward Artificial Neural Network-based on FPGA chip with 32-bit IEEE-754-1985 floating-point number standard to be utilized in real time chaos-based applications. In the first step of the study, 4-D hyper-chaotic system has been numerically modeled on FPGA using Dormand-Prince numeric algorithm. In the second step, the data set (4X10,000) obtained from Matlab-based numeric model has been divided into two parts as training data set (4X8,000) and test data set (4X2,000) to create ANN-based 4-D hyper-chaotic system. A Multi-Layer Feed-Forward ANN structure with 4 inputs and 4 outputs has been constructed for ANN-based 4-D hyper-chaotic system. This structure has only one hidden layer and there are 8 neurons having Tangent Sigmoid activation function used as the activation function in each neuron. 2.58E-07 Mean Square Error (MSE) value has been obtained from the training of ANN-based 4-D hyper-chaotic system. In the third step, after the successful training of ANN-based 4-D hyper-chaotic system, the design of ANN-based 4-D hyper-chaotic system has been carried out on FPGA by taking the bias and weight values of the ANN structure as reference. In this step, at first, Matlab-based Feed-Forward Multi-Layer 4X8X4 network structure has been coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL) to be implemented on FPGA chips. Then, the bias and weight values of the ANN structure has been converted from decimal number system to floating-point number standard and these converted values have been embedded into the network structure. In the last step, the ANN-based 4-D hyper-chaotic system designed on FPGA has been synthesized and tested using Xilinx ISE Design Suite. The chip statistics have been given after the Place&Route process carried out for the Virtex XC6VHX255T-3FF1155 FPGA chip. The maximum operating frequency of ANN-based 4-D hyper-chaotic system on FPGA has been obtained as 240.861 MHZ.
E. Avaroğlu, T. Tuncer, A. B. Özer, B. Ergen, and M. Türk, “A novel chaos-based post-processing for TRNG,” Nonlinear Dyn., vol. 81, no. 1–2, pp. 189–199, Jul. 2015, doi: 10.1007/s11071-015-1981-9.
İ. Koyuncu, M. Tuna, İ. Pehlivan, C. B. Fidan, and M. Alçın, “Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator,” Analog Integr. Circuits Signal Process., vol. 102, pp. 445–456, Dec. 2020, doi: 10.1007/s10470-019-01568-x.
I. Dalkiran and K. Danis, “Artificial neural network based chaotic generator for cryptology,” Comp Sci, vol. 18, no. 2, pp. 225–240, 2010, doi: 10.3906/elk-0907-140.
M. Tuna and C. B. Fidan, “A Study on the importance of chaotic oscillators based on FPGA for true random number generating (TRNG) and chaotic systems,” J. Fac. Eng. Archit. Gazi Univ., vol. 33, no. 2, pp. 469–486, 2018, doi: 10.17341/GUMMFD.71479.
M. Alçın, M. Tuna, and İ. Koyuncu, “IQ-Math Based Designing of Fourth Order Runge-Kutta Algorithm on FPGA and Performance Analysis According to ANN Approximation,” Int. J. Adv. Sci. Eng. Technol., vol. 5, no. 8, pp. 6523–6530, 2018.
A. M. Garipcan and E. Erdem, “Implementation and Performance Analysis of True Random Number Generator on FPGA Environment by Using Non-periodic Chaotic Signals Obtained from Chaotic Maps,” Arab. J. Sci. Eng., vol. 44, no. 11, pp. 9427–9441, 2019, doi: 10.1007/s13369-019-04027-x.
I. Koyuncu, A. T. Ozcerit, and I. Pehlivan, “Implementation of FPGA-based real time novel chaotic oscillator,” Nonlinear Dyn., vol. 77, no. 1–2, pp. 49–59, Jul. 2014, doi: 10.1007/s11071-014-1272-x.
A. D. Pano-Azucena, E. Tlelo-Cuautle, G. Rodriguez-Gomez, and L. G. De La Fraga, “FPGA-based implementation of chaotic oscillators by applying the numerical method based on trigonometric polynomials,” AIP Adv., vol. 8, no. 7, pp. 075217–12, Jul. 2018, doi: 10.1063/1.5038583.
V. Vembarasan and P. Balasubramaniam, “Chaotic synchronization of Rikitake system based on T-S fuzzy control techniques,” Nonlinear Dyn., vol. 74, no. 1–2, pp. 31–44, Oct. 2013, doi: 10.1007/s11071-013-0946-0.
L. Li, Z. Liu, D. Zhang, and H. Zhang, “Controlling chaotic robots with kinematical redundancy.,” Chaos, vol. 16, no. 1, p. 013132, Mar. 2006, doi: 10.1063/1.2178447.
Ü. Çavuşoğlu, S. Kaçar, I. Pehlivan, and A. Zengin, “Secure image encryption algorithm design using a novel chaos based S-Box,” Chaos, Solitons & Fractals, vol. 95, pp. 92–101, Feb. 2017, doi: 10.1016/J.CHAOS.2016.12.018.
M. Alcin, I. Koyuncu, M. Tuna, M. Varan, and I. Pehlivan, “A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array,” Int. J. Circuit Theory Appl., vol. 47, no. 3, pp. 365–378, Mar. 2019, doi: 10.1002/cta.2581.
E. Avaroğlu, İ. Koyuncu, A. B. Özer, and M. Türk, “Hybrid pseudo-random number generator for cryptographic systems,” Nonlinear Dyn., vol. 82, no. 1–2, pp. 239–248, Oct. 2015, doi: 10.1007/s11071-015-2152-8.
U. E. Kocamaz, S. Çiçek, and Y. Uyaroğlu, “Secure Communication with Chaos and Electronic Circuit Design Using Passivity-Based Synchronization,” J. Circuits, Syst. Comput., vol. 27, no. 04, p. 1850057, Apr. 2018, doi: 10.1142/S0218126618500573.
İ. Koyuncu, Y. Oğuz, H. Çimen, T. Özer, and M. Tuna, “Design and Implementation of Artificial Neural Network-Based 3-D Novel Jerk Chaotic Oscillator on FPGA,” 3rd International Conference on Engineering Technology and Applied Sciences, Skopje, Macedonia, pp. 1–6, 2018.
Ü. Çavuşoglu, Y. Uyaroglu, and İ. Pehlivan, “Design of A Continuous-Time Autonomous Chaotic Circuit and Application of Signal Masking,” J. Fac. Eng. Archit. Gazi Univ., vol. 29, no. 1, pp. 79–87, Mar. 2014, doi: 10.17341/gummfd.73592.
M. Tuna, M. Alçın, İ. Koyuncu, C. B. Fidan, and İ. Pehlivan, “High speed FPGA-based chaotic oscillator design,” Microprocess. Microsyst., vol. 66, pp. 72–80, Apr. 2019, doi: 10.1016/J.MICPRO.2019.02.012.
R. A. Elmanfaloty and E. Abou-Bakr, “Random property enhancement of a 1D chaotic PRNG with finite precision implementation,” Chaos, Solitons and Fractals, vol. 118, pp. 134–144, Jan. 2019, doi: 10.1016/j.chaos.2018.11.019.
F. Katırcıoğlu, İ. Koyuncu, M. Kelek, Y. Oğuz, and M. Şen, “FPGA-Based Design of Gaussian Membership Function for Real-Time Fuzzy Logic Applications,” V. International Multidisciplinary Congress Of Eurasia, Barselona, Spain, 2018.
M. Tuna, C. B. Fidan, I. Koyuncu, and I. Pehlivan, “Real time hardware implementation of the 3D chaotic oscillator which having golden-section equilibra,” 2016 24th Signal Processing and Communication Application Conference (SIU), IEEE, Zonguldak, Turkey, pp. 1309–1312, May-2016.
S. Vaidyanathan et al., “A novel ANN-based four-dimensional two-disk hyperchaotic dynamical system, bifurcation analysis, circuit realisation and FPGA-based TRNG implementation,” Int. J. Comput. Appl. Technol., vol. 62, no. 1, pp. 20–35, 2020, doi: 10.1504/IJCAT.2020.103921.
E. Tlelo-Cuautle, J. J. Rangel-Magdaleno, A. D. Pano-Azucena, P. J. Obeso-Rodelo, and J. C. Nunez-Perez, “FPGA realization of multi-scroll chaotic oscillators,” Commun. Nonlinear Sci. Numer. Simul., vol. 27, no. 1–3, pp. 66–80, Oct. 2015, doi: 10.1016/j.cnsns.2015.03.003.
M. Stipcevic, “Quantum random number generators and their applications in cryptography,” Proc. Artic., vol. 8375, no. 2012, pp. 1–6, May 2012, doi: 10.1117/12.919920.
M. Alçın, İ. Pehlivan, and İ. Koyuncu, “Hardware design and implementation of a novel ANN-based chaotic generator in FPGA,” Opt. - Int. J. Light Electron Opt., vol. 127, no. 13, pp. 5500–5505, Jul. 2016, doi: 10.1016/j.ijleo.2016.03.042.
K. Rajagopal, A. Karthikeyan, and A. K. Srinivasan, “FPGA implementation of novel fractional-order chaotic systems with two equilibriums and no equilibrium and its adaptive sliding mode synchronization,” Nonlinear Dyn., vol. 87, no. 4, pp. 2281–2304, Mar. 2017, doi: 10.1007/s11071-016-3189-z.
I. Koyuncu, A. T. Ozcerit, and I. Pehlivan, “An analog circuit design and FPGA-based implementation of the Burke-Shaw chaotic system,” Optoelectron. Adv. Materıals-Rapıd Communıcatıons, vol. 7, no. 9, pp. 635–638, Sep. 2013.
A. Akgul, H. Calgan, I. Koyuncu, I. Pehlivan, and A. Istanbullu, “Chaos-based engineering applications with a 3D chaotic system without equilibrium points,” Nonlinear Dyn., vol. 84, no. 2, pp. 481–495, Nov. 2015, doi: 10.1007/s11071-015-2501-7.
K. Rajagopal, A. Akgul, S. Jafari, A. Karthikeyan, and I. Koyuncu, “Chaotic chameleon: Dynamic analyses, circuit implementation, FPGA design and fractional-order form with basic analyses,” Chaos, Solitons & Fractals, vol. 103, pp. 476–487, Oct. 2017, doi: 10.1016/J.CHAOS.2017.07.007.
M. Tuna and C. B. Fidan, “Electronic circuit design, implementation and FPGA-based realization of a new 3D chaotic system with single equilibrium point,” Opt. - Int. J. Light Electron Opt., vol. 127, no. 24, pp. 11786–11799, 2016, doi: 10.1016/j.ijleo.2016.09.087.
I. Koyuncu, M. Alcin, M. Tuna, I. Pehlivan, M. Varan, and S. Vaidyanathan, “Real-time high-speed 5-D hyperchaotic Lorenz system on FPGA,” Int. J. Comput. Appl. Technol., vol. 61, no. 3, pp. 152–165, 2019, doi: 10.1504/IJCAT.2019.102852.
A. E. Matouk, “Dynamics and control in a novel hyperchaotic system,” in International Journal of Dynamics and Control, 2019, vol. 7, no. 1, pp. 241–255, doi: 10.1007/s40435-018-0439-6.
M. Tuna, C. B. Fidan, and İ. Koyuncu, The Chaos-Based Dual Entropy Core TRNG on FPGA, with VHDL codes of Chaotic Systems. LAP Lambert Academic Publishing, ISBN:978-613-9-9958-3, 2019.
T. Tuncer, “The implementation of chaos-based PUF designs in field programmable gate array,” Nonlinear Dyn., vol. 86, no. 2, pp. 975–986, Oct. 2016, doi: 10.1007/s11071-016-2938-3.
S. Chen, B. Li, and C. Zhou, “FPGA implementation of SRAM PUFs based cryptographically secure pseudo-random number generator,” Microprocess. Microsyst., vol. 59, pp. 57–68, Jun. 2018, doi: 10.1016/j.micpro.2018.02.001.
P. Prakash et al., “A Novel Simple 4-D Hyperchaotic System with a Saddle-Point Index-2 Equilibrium Point and Multistability: Design and FPGA-Based Applications,” Circuits, Syst. Signal Process., pp. 1–22, Feb. 2020, doi: 10.1007/s00034-020-01367-0.
I. Koyuncu, “Design and Implementation of High Speed Artificial Neural Network Based Sprott 94 S System on FPGA,” Int. J. Intell. Syst. Appl. Eng., vol. 4, no. 2, p. 33, May 2016, doi: 10.18201/ijisae.97824.
M. Rana, D. Abdu-Aljabar, and A. Lecturer, “Design and Implementation of Neural Network in FPGA,” J. Eng. Dev., vol. 16, no. 3, pp. 73–90, 2012.
M. Şahin, Y. Oğuz, and F. Büyüktümtürk, “ANN-based estimation of time-dependent energy loss in lighting systems,” Energy Build., vol. 116, pp. 455–467, Mar. 2016, doi: 10.1016/J.ENBUILD.2016.01.027.
S. Sahin, Y. Becerikli, and S. Yazici, “Neural network implementation in hardware using FPGAs,” in Lecture Notes in Computer Science, 2006, vol. 4234 LNCS, pp. 1105–1112, doi: 10.1007/11893295_122.
I. Sahin and I. Koyuncu, “Design and Implementation of Neural Networks Neurons with RadBas, LogSig, and TanSig Activation Functions on FPGA,” Electron. Electr. Eng., vol. 120, no. 4, pp. 51–54, Apr. 2012, doi: 10.5755/j01.eee.120.4.1452.
M. A. Çavuşlu, C. Karakuzu, S. Şahin, and M. Yakut, “Neural network training based on FPGA with floating point number format and it’s performance,” Neural Comput. Appl., vol. 20, no. 2, pp. 195–202, 2011, doi: 10.1007/s00521-010-0423-3.
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