Optimization of CMOS Miller OTA using Differential Evolutionary Algorithm


The circuit parameters of CMOS based analog and mixed-signal circuits conventionally are achieved by skilled engineers. Due to the progress of Moore’s assumption and the growing complication of physical MOSFET models, the attention towards automation of CMOS based analog circuit design is increased. The issue of the automatic design of analog circuit has been tracked in the academy and industry since more than last two decades. In this paper, application of differential evolution (DE) algorithm is presented for the optimization of CMOS Miller Operational Transconductance Amplifier (OTA). DE algorithm has been developed using C language to optimize the CMOS Miller OTA. The error function of optimization for this circuit depends on desired specifications like voltage gain, phase margin (PM), unit gain bandwidth (UGB), power consumption, common mode rejection ratio (CMRR), slew rate (SR), power supply rejection ratio (PSRR), and a total MOS transistor area. Ngspice circuit simulator has been used as an error function creator and evaluator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature


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A. C. Kammara, L. Palanichamy, and A. König, "Multi-objective optimization and visualization for analog design automation," A. Complex Intell. Syst., vol. 2, no. 4, pp. pp 251-267, 2016.

J. Kennedy and R. C. Eberhart, "Particle swarm optimization," in Proceedings IEEE international conference on neural networks, Washington, 1995.

Darwin, Wim Kruiskamp DL, "CMOS OPAMP synthesis by means of a genetic algorithm," in 32nd conference on design automation, DAC ’95, 1995.

R. Stron and K. Price, "Differential evolution- a simple and efficient heuristic for global optimization over continuous spaces," Journal of Global Optimization, vol. 11, no. 4, pp. 341-359, 1997.

Z. W. Geem, J. H. Kim and G. Loganathan, "A new heuristic optimization algorithm: harmony search," Simulation, vol. 76, no. 2, pp. 60-68, 2001.

M. Dorigo, V. Maniezzo and A. Golomi, "Ant system: optimization by a colony of cooperating agent," IEEE Trans. Syst. Man Cybernet, vol. 26, no. 1, pp. 29-41, 1996.

D. Karaboga, "An idea based on honey bee swarm for numerical optimization," Erciycs University, Engineering Faculty, Computer Engineering Dept., Technical Report-TR-06, 2005.

S. Sabat, K. Kumar, and S. Udgata, "Differential evolution and swarm intelligence techniques for analog circuit synthesis 2009," in World congress on nature biologically inspired computing, NaBIC, 2009.

R. Vural and U. Ayten, "Optimized analog filter approximation via evolutionary algorithms," in 12th international conference on intelligent systems design and applications (ISDA), 2012.

S. Kudikala, S. Sabat and S. Udgata, "Performance study of harmony search algorithm for analog circuit sizing," in International symposium on electronic system design (ISED), 2011.

R. A. Thakker, M. Baghini, and M.Patil "Low-power low-voltage analog circuit design using hierarchical particle swarm optimization," in 22nd international conference on VLSI design, 2009.

S. Sharma, and P. P. Prajapati, , "Design of Various Analog Circuits using Differential Evolutionary Algorithm," International Journal of Scientific Progress and Research, vol. 23, no. 3, pp. 159-165, 2016.

P. P. Prajapati and M. V. Shah, Automated Sizing Methodology for CMOS Miller Operational Transconductance Amplifier. In Soft Computing: Theories and Applications, Advances in Intelligent Systems and Computing, vol. 584, pp 301-308, Springer, Singapore, Nov. 2017, DOI.org/10.1007/978-981-10-5699-4_29

S. Patel, and R. A. Thakkar, "Automatic Circuit Design and Optimization using Modified PSO Algorithm," Journal of Engineering Science and Technology Review, vol. 9, no. 4, pp. 192-197, 2016.

P. P. Prajapati, and M. V. Shah, "Two Stage CMOS Operational Amplifier Design Using Particle Swarm Optimization Algorithm," in IEEE UP Section Conference on Electrical Computer and Electronics, 2015.

L. Ferreira, C. P. Tales, and L. M. Robson, "An ultra-low-voltage ultra-low-power CMOS Miller OTA with rail-to-rail input/output swing," in IEEE Cir. and Sys.-II: Exp. Briefs, 2007.

H. D. Dammak, S. Bensalem, S. Zouari, and M. Loulo, "Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology," World Academy of Science,Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, vol. 2, no. 9, pp. 174-176, 2008.

M. Akbari, M. Shokouhifar, O. Hashemipour, et al., "Systematic design of analog integrated circuits using ant colony algorithm based on noise optimization," Analog Integr. Circ. Sig. Process., vol. 86, no. 2, pp. 327-339., 2016.

Arunachalam V, "Optimization using Differential Evolution,” Facility for Intelligent Decision Support, Department of Civil and Environmental Engineering, London, Ontario, Canada., Water Resources Research Report no. 60, 2008.

S. Dasgupta, S. Das, A. Biswas, and A. Abraham, "On Stability and Convergence of the Population-Dynamics in Differential Evolution," The European Journal on Artificial Intelligence, vol. 1, pp. 1-20, 2009.

H. Gupta and B.Ghosh "Analog Circuits Design using Ant Colony Optimization," IJECCT, vol. 2, pp. 9-21, 2012.

How to Cite
P. Prajapati, K. Acharya, and M. Shah, “Optimization of CMOS Miller OTA using Differential Evolutionary Algorithm”, IJISAE, vol. 7, no. 1, pp. 47-51, Mar. 2019.
Research Article