Noise Immune Schmitt Trigger Logic Gate Based Disturb Free Scalable 9T SRAM In Memory Computing Design - Mucherla Usha Rani (International Journal of Intelligent Systems and Applications in Engineering, 2024)
In Von Neumann’s architecture, memory serves as a storage component, whereas the arithmetic logic unit (ALU) serves as a computation device. However, when a lot of data flows between the memory and the ALU, Von Neumann bottlenecks remain a serious problem, resulting in limitations related to temporal overhead, throughput, and energy efficiency. This paper develops an In-memory computing (IMC) structure for computing ripple carry addition and multiplication (RCA-M) processes directly in the memory array. Here, Half-Select Disturb-Free Write Assist (HDFWA) Static random-access memories (SRAM) cell is designed with 9 transistors to optimize the read and write static noise margin (SNM) individually. The current compensation based sensor circuit is used to reduce leakage power and improve reading performance. In addition, the control circuits of the proposed IMC architecture, including SRAM control, IMC control, and RCA-M, are designed using Schmitt trigger (ST) logic to enable noise-immune, reliable, and efficient IMC systems. By using the ST logic, switching power is greatly reduced, and noise immunity is increased. The simulation outputs demonstrate that the suggested IMC for RCA-M outperforms other IMC architectures in terms of average energy efficiency (4.019 fJ) on CMOS 14nm technology.