ERNA, G. .; SAIDULU, V. .; SRIHARI, G. .; RAO, K. B. . FPGA Implementation of Adaptive Hold Logic Vedic Fused Dot Product Floating-Point Multiplier Using Razor Flip -Flop. International Journal of Intelligent Systems and Applications in Engineering, [S. l.], v. 12, n. 2s, p. 420–434, 2023. Disponível em: https://ijisae.org/index.php/IJISAE/article/view/3642. Acesso em: 22 jul. 2024.