M. S., N. .; A. M., V. P. . Design and Implementation of High Speed, Low Power LVDS Receiver Architecture in 18nm FINFET Process Technology. International Journal of Intelligent Systems and Applications in Engineering, [S. l.], v. 12, n. 15s, p. 229–239, 2024. Disponível em: https://ijisae.org/index.php/IJISAE/article/view/4738. Acesso em: 22 jul. 2024.