NADDUNOORI, M. .; M. , D. . Design of an Error Detection Fault Tolerant Arbiter for a Network on Chip. International Journal of Intelligent Systems and Applications in Engineering, [S. l.], v. 12, n. 18s, p. 670–681, 2024. Disponível em: https://ijisae.org/index.php/IJISAE/article/view/5022. Acesso em: 22 jul. 2024.