ANURADHA M. SANDI, G. N. S. . A Low-Latency, Area-Efficient Convolution Network for FPGA Acceleration. International Journal of Intelligent Systems and Applications in Engineering, [S. l.], v. 12, n. 3, p. 767–775, 2024. Disponível em: https://ijisae.org/index.php/IJISAE/article/view/5355. Acesso em: 22 jul. 2024.