T ADITHYA NAG VENKAT. A Low-delay Configurable Register for FPGA using GDI Technique. International Journal of Intelligent Systems and Applications in Engineering, [S. l.], v. 12, n. 3, p. 3799–3805, 2024. Disponível em: https://ijisae.org/index.php/IJISAE/article/view/6056. Acesso em: 22 jul. 2024.