SATHYANARAYANA, R. .; RAMASWAMY , N. K. .; RAMASWAMY, R. K. . An Efficient Low-Power Reconfigurable Model For CMOS-Based SRAM Using FPGA. International Journal of Intelligent Systems and Applications in Engineering, [S. l.], v. 12, n. 1, p. 500–515, 2023. Disponível em: https://ijisae.org/index.php/IJISAE/article/view/3948. Acesso em: 20 may. 2024.