Anuradha M. Sandi GNS. A Low-Latency, Area-Efficient Convolution Network for FPGA Acceleration. Int J Intell Syst Appl Eng [Internet]. 2024 Mar. 16 [cited 2025 Nov. 16];12(3):767-75. Available from: https://ijisae.org/index.php/IJISAE/article/view/5355