Design of High-Performance GDI Logic based 8-Tap FIR Filter at 45nm CMOS Technology using Nikhilam Multiplier

Authors

  • Bindu Swetha Pasuluri Research Scholar, School of Electrical and Electronics Engineering, Sathyabama Institute of Science & Technology, Chennai-600119, India
  • V.J.K. Kishor Sonti Assoc. Professor, School of Electrical and Electronics Engineering, Sathyabama Institute of Science & Technology, Chennai-600119, India

Keywords:

GDI technique, FIR filter design, MAC, Multiplier, Full adder

Abstract

Over the past few decades, advances in IC technology have steadily shrunk feature sizes, necessitating the placement of more operational circuits on every chip. In designing digital circuits, a novel GDI based circuit is indeed the center of consideration, since it requires less power and achieves greater efficiency. GDI-based circuits mimic CMOS transistors but feature fewer transistors with a greater capacity for performance and reliability. This paper investigates the modelling and implementation of a Finite Impulse-Response (FIR) block developed utilizing GDI-based circuits as well as basic blocks. In this study, an eight-tap FIR architecture relying on GDI cells is created. The results reveal that even a FIR architecture with eight taps and GDI delivers reduced power consumption and performance improvement.

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FIR Structure in Direct Form

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Published

01.10.2022

How to Cite

Pasuluri, B. S. ., & Sonti, V. K. . (2022). Design of High-Performance GDI Logic based 8-Tap FIR Filter at 45nm CMOS Technology using Nikhilam Multiplier. International Journal of Intelligent Systems and Applications in Engineering, 10(3), 340–346. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/2174

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Research Article