Design an Efficient Braun Multiplier Using KSA Based CMOS Logics

Authors

  • Daphni S Research Scholar Department of Electronics and Communication Engineering, NICHE, Tamilnadu, India
  • Vijula Grace K. S Associate Professor Department of Electronics and Communication Engineering, NICHE, Tamilnadu, India
  • Judith Johnsi J Computer Science department, Indian School Al Mabella, Muscat, Sultanate of Oman
  • Bamini S Applied Electronics (M.E), Bangalore, India

Keywords:

Parallel Prefix Adder, Braun Multiplier, Complementary Inverter logic, Kogge Stone Adder, Pass Transistor Logic

Abstract

The addition is the basic process of digital electronics in DSP and VLSI processing applications.  In earlier days, many researchers have developed various binary adders and technologies have used to precede the addition process in digital electronic applications. Half and Full Adders are the two fundamental binary adders with limited to the addition up to 3 bits. If the addition required more than 4 bits, then the basic HA and FA adders has not suitable. In that situation, the binary addition process has done with the help of high grade binary carry adders such as RCA, CSA, CSLA, CLA. Due the carry delay problem, the Parallel Prefix Adder (PPA) has selected as the high speed adder to do the binary addition with less delay by researched developers. Generally, the addition is used to implement the binary multiplication process in digital electronics. This paper has proposed the design of Braun Array Multiplier (BAM) using Kogge Stone Parallel Prefix Adder based CMOS logics. Belongs to that, this work has proposed the KSA based Pass Transistor logic, NMOS with Complementary Inverter logic and PMOS with Complementary Inverter logic. All the logics have applied in the Braun Array Multiplier to enhance the performance of multiplication process. The proposed logics have compared with the aspects like area, power and layout size. Microwind tool is able to generate the simulation and analysis results.

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References

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Execution results of proposed Pass Transistor logic based KSA

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Published

01.10.2022

How to Cite

S, D. ., K. S, V. G. ., Johnsi J, J., & S, B. . (2022). Design an Efficient Braun Multiplier Using KSA Based CMOS Logics. International Journal of Intelligent Systems and Applications in Engineering, 10(3), 423–429. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/2183

Issue

Vol. 10 No. 3 (2022)

Section

Research Article

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