A Leakage Reduction Charge Pump based Domino Logic for Low Power VLSI Circuits
Keywords:
Charge pump, domino logic, leakage reduction, Low power VLSIAbstract
A new leakage reduction domino logic circuit with a charge pump and a transistor is proposed to improve the performance of the high fan-in circuits. The charge pump and two parallel connected transistors are used to improve the signal strength of the output and reducing the delay. Keeper transistor is used to restore the logic levels of the node. An additional transistor is used to reduce the leakage currents and reducing the power dissipation. The proposed circuit is also applied for domino OR logic function. The proposed technique has a lesser delay and power dissipation compared to the standard domino logic. The proposed technique is more suitable for high speed and low power domino OR logic and can be implemented to the high fan-in gates.
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