Memory Optimization Using Distributed Shared Memory Management for Re-engineering
Keywords:
Memory management, Power Consumption, Shared distributed memory (SDM), Memory mapping Mechanism, Re-engineeringAbstract
Restructure the old input C++ programming system to make it suitable for reengineering, which necessitates humongous memory. This study has made significant contributions to the disciplines of system-on-chip design and on-chip memory management, among others. This paper presents a new technique for optimizing memory subsystems during system design that is suited to specific applications like re-engineering. This work can be improved to optimize memory controller activities and design challenges for distributed shared memory management. It has the capacity to manage an increasing number of processors simultaneously, as well as security and faster execution. The Xilinx 14.2 integrated simulation environment produces outstanding results when the proposed memory optimization approaches are fully integrated into the simulation, optimization, and code generation cycle. The proposed memory device has an extremely low on-chip power consumption of 0.0082 W, which amply demonstrates how well memory has been improved.
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Ahmed, M.R., Zheng, H., Mukherjee, P., Ketkar, M.C. and Yang, J., 2021, April. Mining message flows from system-on-chip execution traces. In 2021 22nd international symposium on quality electronic design (ISQED) (pp. 374-380). IEEE.
Shan, L. and Sun, H., 2021, May. Distributed collaborative simulation middleware based on reflective memory network. In 2021 IEEE 24th international conference on computer supported cooperative work in design (CSCWD) (pp. 274-279). IEEE.
Cao, Y., Mukherjee, P., Ketkar, M., Yang, J. and Zheng, H., 2020, March. Mining message flows using recurrent neural networks for system-on-chip designs. In 2020 21st International Symposium on Quality Electronic Design (ISQED) (pp. 389-394). IEEE.
Adetomi, A., Enemali, G. and Arslan, T., 2017, September. Towards an efficient intellectual property protection in dynamically reconfigurable FPGAs. In 2017 Seventh International Conference on Emerging Security Technologies (EST) (pp. 150-156). IEEE.
Wen, H. and Zhang, W., 2021. Cache Leakage Reduction Techniques for Hybrid SPM-Cache Architectures. Journal of Circuits, Systems and Computers, 30(01), p.2150008.
Kwon, S.J., Kim, S.H., Kim, H.J. and Kim, J.S., 2017, January. LZ4m: A fast compression algorithm for in-memory data. In 2017 IEEE International Conference on Consumer Electronics (ICCE) (pp. 420-423). IEEE.
Guo, Y., Hua, Y. and Zuo, P., 2018, March. DFPC: A dynamic frequent pattern compression scheme in NVM-based main memory. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1622-1627). IEEE.
Choukse, E., Erez, M. and Alameldeen, A.R., 2018, October. Compresso: Pragmatic main memory compression. In 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (pp. 546-558). IEEE.
Lahiry, A. and Kaeli, D., 2017, November. Dual dictionary compression for the last level cache. In 2017 IEEE International Conference on Computer Design (ICCD) (pp. 353-360). IEEE.
Rumyantsev, A., Krupkina, T., Losev, V. and Maksimov, A., 2020, January. Development of a Measurement System-on-Chip and Simulation on FPGA. In 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) (pp. 1851-1854). IEEE.
Frolova, P.I., Chochaev, R.Z., Ivanova, G.A. and Gavrilov, S.V., 2020, January. Delay matrix based timing-driven placement for reconfigurable systems-on-chip. In 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) (pp. 1799-1803). IEEE.
Jain, A., Soner, S. and Holkar, A., 2010, October. “Reverse engineering”: Extracting information from C++ code. In 2010 2nd International Conference on Software Technology and Engineering (Vol. 1, pp. V1-154). IEEE.
Strobel, M., Radetzki, M.: Design-time memory subsystem optimization for lowpower multi-core embedded systems. In: 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp. 347–353 (2019). DOI 10.1109/MCSoC.2019.00056.
H. Fan et al., "High-Precision Adaptive Slope Compensation Circuit for System-on-Chip Power Management," 2019 IEEE 38th International Performance Computing and Communications Conference (IPCCC), 2019, pp. 1-2.
N. Arun Vignesh, Ravi Kumar, R. Rajarajan, S. Kanithan, E. Sathish Kumar, Asisa Kumar Panigrahy, and Selvakumar Periyasamy, “Silicon Wearable Body Area Antenna for Speech-Enhanced IoT and Nanomedical Applications”, Journal of Nanomaterials, vol. 2022 , Article ID 2842861, 9 pages, 2022. https://doi.org/10.1155/2022/2842861
Devi, M.P., Ravanan, V., Kanithan, S., N.A.Vignesh, “Performance Evaluation of FinFET Device Under Nanometer Regime for Ultra-low Power Applications”, Silicon (2022). https://doi.org/10.1007/s12633-022-01772-x
D. Chen, J. Edstrom, Y. Gong, P. Gao, L. Yang, M. McCourt, J. Wang and N. Gong, "Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 4, pp. 684-696, 2018.
Calinescu, G., Fu, C., Li, M., Wang, K. and Xue, C.J., 2018. Energy optimal task scheduling with normally-off local memory and sleep-aware shared memory with access conflict. IEEE Transactions on Computers, 67(8), pp.1121-1135.
Arun Jayakar, S., Rajesh, T., Vignesh, N.A. and Kanithan, S., 2022. Performance Analysis of Doping Less Nanotube Tunnel Field Effect Transistor for High Speed Applications. Silicon, 14(12), pp.7297-7304.
Z. Zhao, Y. Sheng, M. Zhu and J. Wang, "A Memory-Efficient Approach to the Scalability of Recommender System With Hit Improvement", IEEE Access, vol. 6, pp. 67070-67081, 2018.
Deepa, R., Devi, M.P., Vignesh, N.A. and Kanithan, S., 2022. Implementation and performance evaluation of ferroelectric negative capacitance FET. Silicon, 14(5), pp.2409-2419.
Handigund, S.M. and Kulkarni, R.N., 2010. An Ameliorated Methodology for the design of Object Structures from legacy ‘C’Program. International Journal of Computer Applications, 975, p.8887.
Dr. Shivanand M. Handigund, Dr. Rajkumar N. Kulkarni, “An Ameliorated Methodology for the Abstraction and Minimization of Functional Dependencies of legacy ‘C’ Program Elements “. International Journal of Computer Applications (0975 – 8887) Volume 16– No.3, February 2011.
Dr. R.N. Kulkarni, Venkata Sandeep Edara, "A Novel Approach to Restructure The Legacy C++ Program", Journal of Huazhong University of Science and Technology, Volume: 50 Issue: 05 , 2021, ISSN: 1671-4512.
Dr. R.N. Kulkarni, P.Pani Rama Prasad, "Abstraction of UML Class Diagram from the Input Java Program", Int. J. Advanced Networking and Applications, Volume: 12 Issue: 04 Pages: 4644-4649(2021) ISSN: 0975-0290.
R.N.Kulkarni and S.Shenaz Begum, "Abstraction of 'C' Program from Algorithm", Springer Nature Singapore Pte Ltd. 2021, Research in Intelligent and Computing in Engineering, Advances in Intelligent Systems and Computing 1254.
Nair, K. S. S. . (2023). Rapidly Convergent Series from Positive Term Series. International Journal on Recent and Innovation Trends in Computing and Communication, 11(3), 79–86. https://doi.org/10.17762/ijritcc.v11i3.6204
Ana Silva, Deep Learning Approaches for Computer Vision in Autonomous Vehicles , Machine Learning Applications Conference Proceedings, Vol 1 2021.
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