Novel Test Point Insertion Mechanism Using Timing Aware Analysis to Target the Challenges in High Complex SOC Designs
Keywords:
Control nodes, Observe nodes, Test point insertion, TPI, Static timing analysis (STA), critical paths, pattern countAbstract
The modern complex, SoC designs use Advanced fault modelling like Cell-Aware-Test (CAT), Automotive fault grading (AGF), and Path delay fault models to cover all the possible potential defects in the design. Due to this advanced fault modelling the coverage is reduced and test vector volume increased drastically around 3x-4x times Compared to the standard ATPG approach. It impacts the reliability, overall testing cost and test time of the design. Test point Insertion (TPI) is the optimal solution to overcome the lower coverage and high volume of vector count issues by providing the controllable and observable nodes in the design to cover the uncontrollable and unobservable nodes. TPI is the methodology to identify the areas in a design which has low testability and require more patterns to achieve the targeted test coverage. At the same time, Test Point Insertion will lead to significant area impact and timing critical challenges after synthesis and post-optimization process. To overcome the Area and critical path timing challenges we proposed a Novel Test point Insertion mechanism by using the static timing Analysis (STA) Approach. In this approach, we calculated the most effective test points by using timing aware analysis followed by fault simulations. Based on the coverage, fault count and area overhead target optimal % of inefficient test points is discarded during the final TPI implementation. Finally, effective timing aware TPIs are inserted in the design to overcome the above mentioned challenges. The experiments are performed on the various design blocks, and the results are compared with conventional TPI approaches w.r.t area impact, pattern volume and coverage. It proves that the proposed Test Point Insertion approach gives a significant improvement in TPI area overhead reduction around 75% and the test vector count reduced to 48% with minimal coverage loss as low as 0.2%.
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