Design and Analysis of Low Power VLSI based SRAM Cell using CMOS, FinFET and GNRFET Technologies

Ramesh  Gullapally; N. Siva Sankara  Reddy; P. Chandra  Sekhar

Authors

Ramesh Gullapally Research Scholar, Department of Electronics and Communication Engineering, University College of Engineering, Osmania University, Hyderabad
N. Siva Sankara Reddy Associate Professor, Department of Electronics and Communication Engineering, Vasavi College of Engineering, Hyderabad
P. Chandra Sekhar Professor, Department of Electronics and Communication Engineering, University College of Engineering, Osmania University, Hyderabad

Keywords:

CMOS, GNRFET, VLSI, SRAM, HSpice

Abstract

Graphene nanoribbon field-effect transistors (GNRFETs) has the ability to be processed and fabricated on a massive scale, making them a viable device for beyond-CMOS nanoelectronics. The primary focus of this study is the design of an SRAM cell using 10 transistors and taking into account two different threshold values. Research efforts centered on FinFET and GNRFET during circuit design. Despite claims of higher performance, lower power consumption, and identical reliability at comparable operating points to scaled CMOS circuits, simulation studies demonstrate that GNRFET circuits are more susceptible to variations and errors. The device and CAD groups working with graphene have some difficult engineering, modeling, and simulation problems to solve as a consequence of these results.

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References

Mihir R. Choudhury, Student Member, IEEE, Youngki Yoon, Member, IEEE, Jing Guo, Member, IEEE, and Kartik Mohanram, Member, IEEE “Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability”, IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011

Divya Geethakumari Anil, Yu Bai and Yoonsuk Choi, “Performance Evaluation of Ternary Computation in SRAM Design Using Graphene Nanoribbon Field Effect Transistors” 978-1-5386-4649-6/18/ ,2018, IEEE

Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell”, IEEE Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV), January 2015.

S. Lin, Y. B. Kim, and F. Lombardi, “CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits”, IEEE Transactions on Nanotechnology, Vol. 10, No. 2, March 2011.

P. Wessely, F. Wessely, E. Birinci, U. Schwalke, and B. Riedinger, “Transfer-free Fabrication of Graphene Transistors,” J. Vac. Sci. Technol. B 30, 2012.

A. Murugesan, “A Theoretical description of Graphene based Transistors”, IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 3, May 2014.

A. Imran, R. S. Singh, M. Mishra, “Simulation Study of Logic Circuits using Optimized Graphene Nanoribbon Fets “, 2016 2nd International Conference on Next Generation Computing Technologies (NGCT-2016) Dehradun, India 14-16 October 2016.

R. T. Greenway, K. Jeong, A. B. Kahng, C. H. Park, and J. S. Petersen,”332nm 1-D Regular Pitch SRAM Bitcell Design for Interference- Assisted Lithography”, Proceedings Volume 7122, Photomask Technology 2008

K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov, “Electric field effect in atomically thin carbon films,” Science, vol. 306, pp. 666–669, 2004.

Y. Zhang, Y.-W. Tan1, H. L. Stormer, and P. Kim, “Experimental observation of the quantum Hall effect and Berry’s phase in graphene,” Nature, vol. 438, pp. 201–204, 2005.

C. Berger, Z. Song, X. Li, X. Wu, N. Brown, C. Naud, D. Mayou, T. Li, J. Hass, A. N.Marchenkov, E. H. Conrad, P. N. First, andW. A. de Heer, “Electronic confinement and coherence in patterned epitaxial graphene,” Science, vol. 312, pp. 1191–1196, 2006.

R. V. Noorden, “Moving towards a graphene world,” Nature, vol. 442, pp. 228–229, 2006.

A. K. Geim and K. S. Novoselov, “The rise of graphene,” Nature Mater., vol. 6, pp. 183–191, 2007.

W. A. de Heer, C. Berger, E. Conrad, P. First, R. Murali, and J. Meindl, “Pionics: The emerging science and technology of graphene-based nanoelectronics,” in Intl. Electron Devices Meeting Tech. Dig., 2007, pp. 199– 202.

Z. Chen, Y.-M. Lin,M. J. Rooks, and Ph. Avouris, “Graphene nano-ribbon electronics,” Physica E: Low-dimensional Syst. Nanostruct., vol. 40, pp. 228–232, 2007.

M. Y. Han, B. O¨ zyilmaz, Y. Zhang, and P. Kim, “Energy band-gap engineering of graphene nanoribbons,” Phys. Rev. Lett., vol. 98, pp. 206805- 1–206805-4, 2007.

X. Li, X. Wang, L. Zhang, S. Lee, and H. Dai, “Chemically derived, ultra smooth graphene nanoribbon semiconductors,” Science, vol. 319, pp. 1229–1232, 2008.

Y.-W. Son, M. L. Cohen, and S. G. Louie, “Energy gaps in grapheme nanoribbons,” Phys. Rev. Lett., vol. 97, pp. 216803-1–216803-4, 2006.

K. S. Novoselov et al., “Electric field effect in atomically thin carbon films,” Science, vol. 306, pp. 666–669, 2004.

Y. Zhang et al., “Experimental observation of the quantum Hall effect and Berry’s phase in graphene,” Nature, vol. 438, pp. 201–204, 2005.

C. Berger et al., “Electronic confinement and coherence in patterned epitaxial graphene,” Science, vol. 312, pp. 1191–1196, 2006.

R. V. Noorden, “Moving towards a graphene world,” Nature, vol. 442, pp. 228– 229, 2006.

X. Li et al., “Chemically derived, ultrasmooth graphene nanoribbon semiconductors,” Science, vol. 319, pp. 1229–1232, 2008.

Niraj K. Jha, Deming Chen, “Nanoelectronic Circuit Design", Springer, 2011.

C. R. Manoj, Meenakshi Nagpal, Dhanya Varghese, and V. Ramgopal Rao, " Device Design and Optimization Considerations for Bulk FinFETs", IEEE transactions on electron devices, Vol. 55, No. 2, pp. 609-615, February 2008.

Joerg Appenzeller, "Carbon nanotubes for high performance electronics - Progress and prospect", Purdue e-Pubs, 2008.

Sang Hoon Chae, Young Hee Lee, “Carbon NanoTubes and graphene towards soft electronics,” Nano Convergence 2014, pp.1-15.

Narender Hanchate & N. Ranganathan, (2004),’A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors”, Proceedings of the 17th International Conference on VLSI Design (VLSID”04) IEEE.