Dual Arbiter PUF with Shift Register Based TRNG on Basys-3 FPGA Board and its Performance Analysis on Uniqueness, Reliability and Randomness
Keywords:
Physically Unclonable Function, FPGA, Hardware security, Arbiter PUFAbstract
Hardware security has become a crucial issue as a result of the semiconductor industry's explosive growth and globalization. Various attacking and tampering methods are continuously devised to intrude the current methods of hardware security and protection. Physical Unclonable Functions (PUFs) is a well-known solution for these threats. Hence, many researchers are in deep search for advancing the sequence generator based on different Physical Unclonable Functions (PUFs), trying to improve their reliability, uniqueness & randomness. In this paper, Shift Register based Dual arbiter PUF (SR-APUF) is designed and implemented on Basys-3 Field Programmable Gate Array (FPGA) board and the drawbacks of existing PUF designs in certain areas are improvised finding the reason behind it. In addition to the architecture suggested in this paper, a complication method is also used to increase security. In this proposed SR-APUF, shift register will be controlled by a random number generated by delay lines of the PUF and one-time programmable memory device, which cannot be reconfigure later by attackers and so enhance the security. The responses generated are analyzed by implementing the proposed design of SR-APUF and the experimental results demonstrate a better uniqueness of 47.3%, compare to other FPGA-based APUF. Additionally, a reliability rate of 95.7% is attained. And its randomness is also good as it passes the NIST test.
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