Time Efficient FPGA Overlay for Compute Intensive JPEG Compression Blocks for Real Time Applications
Keywords:
FPGA, synthesize, overlay, empowering, programmable, compressionAbstract
OpenCV functions are quite intensive in terms of computations, making them inappropriate for real-time embedded processor-based architectures for the reason that they have a fixed clock frequency and inadequate memory. A primary motivation for using FPGA overlays for the compute-intensive part of JPEG compression is that it can lead to fast compile time and OpenCV functions can be used in embedded systems. This study intends to synthesize the compute-intensive block of the standard JPEG compression algorithm on PYNQ-Z2 (Xilinx’s Python productivity board), which has ZYNQ 7000 SoC-mixed programmable device that integrates a multi-core processor and an FPGA, providing a compelling platform for IoT, AI, and ML applications and the bit stream generated (overlay) is imported into Python as a hardware library. Application developers who are acquainted with software APIs can take advantage of adaptive computing platforms using the hardware library for the fast development of applications without needing to employ ASIC-style design tools to design hardware. This paper presents the role of the overlay by giving a performance comparison of the OpenCV function on processor-based and FPGA platforms in the form of a custom overlay, empowering general-purpose FPGA applications.
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