Ultra Efficient Reversible Logic Multiplier Design and Implementation for Low Power Application
Keywords:
Reversible Logic, Low power, Adder, Multiplier design, Ancilla bits, Garbage outputsAbstract
In recent years reversible logic has appeared as one of the most encouraging research fields. It has found application in a variety of technologies including low-power CMOS, nano-computing and optical computing etc. It is well known that reversible logic work with future computing technologies that almost emit less heat with negligible power dissipation. This research paper gives the in-depth comparative analysis and design of the different circuits that can be for DSP processor design for low power application using the reversible logic. Paper basically focused on the modified transistorized design and implementation of basic gate like Toffoli Gate, proposed gate like HAG,FAG, FAG1, Half adder and Full adder design, 2*2 multiplier, 4*4 multiplier design and its comparison for the different parameter such as number of transistor required, Gate count, Power Dissipation. In comparative analysis of 4*4 multiplier average power dissipation is found to be 120uW that gives enormous amount of power reduction in the proposed design as compared to existing design available. Design and simulation is done using Tanner EDA tool V13 with 180nm technology file.
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