Design and FPGA Implementation of FREDO-3D-NoC for Low Power and High Throughput and its Protocol Interfacing
Keywords:
Wormhole switching algorithm, 3D-NoC, for exact direction order algorithm Flexible Routing, Buffer and Bufferless, Virtual Cut through (VCT)Abstract
In the past 10 years, Network-On-Chips (NOC) is likely offered solution for future systems on chip design. It gives huge scalability compared to the shared bus-based interconnection and permits more processors to run concurrently since NOC has a custom built wires, we can able to foretell the performance.
Objectives: Within this frame of reference, using Flexible Routing for exact direction order (FREDO) for 5x5 with three layers and 3x3 with three layers we recommended a 3D- NoC for buffer and bufferless. Using Wormhole switching and a Stall-and-Go flow control scheme for buffer and bufferless, the mesh topology is used by the recommended design. Despite of having the advantages of FREDO-NoC over the shared bus system, it has got few constraints, like low throughput, high-cost communication and high-power consumption. To avoid these constraints, we recommend a 3D-NoC (3D FREDO-NoC), the expansion of our 3D FREDO-NoC.
Methods: In this document, the 3D FREDO -NoC architecture is narrated in detail and the output of preliminary evaluation. To meet the prerequisites of performance, power and area, it is required to design routers. This is the core of the network on chips. Few techniques lead to improve the number of buffers to upgrade performance, but it is also liable for a higher portion of the router power and area. The performance of the Router is improved in terms of upgrading the saturation rate by maintaining the constant amount of buffers as the Base Router in the Flexible Router architecture. Findings: Furthermore, it is evident that the flexible Router outperforms the base router in throughput by 23.1%, latency by 31.5% and 9% increase in saturation point for uniform random traffic at higher injection rates.
Novelty: In this document, to prove the functionality and judge the performance compared to the base router it focuses on hardware implementation and evaluation of flexible Router. Here we utilize the Verilog HDL on the considering uniform, hotspot traffic patterns and neighbour to get the cycle precise NoC Simulation system.
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References
Thomas Moscibroda.at.al, “A Case for Bufferless Routing in On-Chip Networks”, ISCA’09, June 20–24, 2009, Austin, Texas, USA.Copyright 2009 ACM 978-1-60558-526-0/09/06
Juan Fang.at.al, “Hybrid Network-on-Chip: An Application-Aware Framework for Big Data”, Hindawi, Complexity Volume 2018, Article ID 1040869, 11 pages,
https://doi.org/10.1155/2018/1040869
Jing Lin.at.al, “Making-a-stop: A new bufferless routing algorithm for on-chip network”, J. Parallel Distrib. Comput. 72 (2012) 515–524, 2012 Elsevier Inc.
Rose George Kunthara.at.al, “ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs”, 978-1-5386-6575-6 /18, 2018 IEEE
Alexander Shpiner.at.al, “On the Capacity of Bufferless Networks-on-Chip”, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2015
Yu-Hsiang Kao.at.al, “Design of A Bufferless Photonic Clos Network-on-Chip Architecture”, IEEE TRANSACTIONS ON COMPUTERS, Digital Object Indentifier 10.1109/TC.2012.250 0018-9340/12, 2012.
Chaochao Feng.at.al, “Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Digital Object Identifier 10.1109/TVLSI.2012.2204909, 1063–8210, 2012 IEEE
Dominic DiTomaso.at.al, “Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures”, IEEE TRANSACTIONS ON COMPUTERS, information: DOI 10.1109/TC.2015.2401013, IEEE Transactions on Computers, 0018-9340 , 2015 IEEE.
Anh T. Tran.at.al, “Achieving High-Performance On-Chip Networks With Shared-Buffer Routers”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 0.1109/TVLSI.2013.2268548, 1063-8210, 2013 IEEE.
1063-8210/$31.00 © 2013 IEEE.at.al, “System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design”, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006.
Chih-Hao Chao.at.al, “Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013.
Mohammad Arjomand and Hamid Sarbazi-Azad, “Power-Performance Analysis of Networks-on-Chip with Arbitrary Buffer Allocation Schemes”, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 10, OCTOBER 2010.
Cunlu Li.at.al, “RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router”, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 1045-9219, 2018 IEEE.
Chun-Wei Wu.at.al, “ A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip”, IEEE TRANSACTIONS ON COMPUTERS, MANUSCRIPT ID: TC-2017-11-0610-R1, 0018-9340, 2018 IEEE.
Davide Zoni.at.al, “CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs”, 10.1109/TPDS.2015.2468716, IEEE Transactions on Parallel and Distributed Systems, 1045-9219, 2015 IEEE
Yu-Yin Chen, at.al, "Path-Diversity-Aware Fault-Tolerant Routing Algorithm for NOC systems", IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 10.1109/TPDS.2016.2588482, 1045-9219, 2016 IEEE.
Anastasios Psarras.at.al, "Networks-on-Chip With Double-Data-Rate Links",IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, 10.1109/TCSI.2017.2734689, 1549-8328, 2017 IEEE.
Zhiliang Qian.at.al, "FSNoC: A Flit-Level Speedup Scheme for Networkon-Chips Using Self-Reconfigurable Bidirectional Channels", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 10.1109/TVLSI.2014.2351833, 1063-8210, 2014 IEEE
Lei Yang.at.al, "Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM based Router", IEEE TRANSACTIONS ON COMPUTERS, 10.1109/TC.2018.2864749, 0018-9340, 2018 IEEE
Feiyang Liu.at.al, "Wavelength-Reused Hierarchical Optical Network on Chip Architecture for Manycore Processors", DOI 10.1109/TSUSC.2017.2733551, IEEE Transactions on Sustainable Computing, 2377-3782, 2017 IEEE
Michael Opoku Agyeman.at.al, "Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation", 10.1109/TPDS.2015.2457444, IEEE Transactions on Parallel and Distributed Systems, 2015.
Alexandre Coelho.at.al, "FL-RuNS: A High-Performance and Runtime Reconfigurable Fault-Tolerant Routing Scheme for Partially Connected Three-Dimensional Networks on Chip", IEEE TRANSACTIONS ON NANOTECHNOLOGY, 1536-125X, Volume 18, 2019.
Haseeb Bokhari and Sri Parameswaran, Network-on-Chip Design, Springer Science+Business Media Dordrecht 2017 S. Ha, J. Teich (eds.), Handbook of Hardware/Software Codesign, DOI 10.1007/978-94-017-7267-9_16.
Assad Abbas.at.al, "A survey on energy-efficient methodologies and architectures of network-on-chip", Computers and Electrical Engineering, ttp://dx.doi.org/10.1016/j.compeleceng.2014.07.012, 0045-7906/2014 Elsevier Ltd.
Ahmed Aldammas.at.al, "The efficiency of buffer and buffer-less data-flow control schemes for congestion avoidance in Networks on Chip", Journal of King Saud University Computer and Information Sciences, 2016, 28, 184–198, http://dx.doi.org/10.1016/j.jksuci.2015.11.002, 1319-1578,Production and hosting by Elsevier B.V.
Armin Runge, "FaFNoC: a Fault-tolerant and Bufferless Network-on-chip", Procedia Computer Science 56 ( 2015 ) 397 – 402, 2015.
Chris Fallin.at.al, "MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect".
Gnaneswara Rao Jonna.at.al, "Minimally Buffered Single-Cycle Deflection Router", 978-3-9815370-2-4/DATE14/2014 EDAA.
George Nychis.at.al, On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-Core Interconnects, SIGCOMM’12, August 13–17, 2012, Helsinki, Finland. Copyright 2012 ACM 978-1-4503-1419-0/12/08
Marwa Shaheen.at.al, "Modified CONNECT: New Bufferless Router for NoC-Based FPGAs", 978-1-5386-7392-8/18, 2018 IEEE
Michael Opoku Agyeman.at.al, "Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity", Journal of Low Power Electronics and Applications, www.mdpi.com/journal/jlpea, Appl. 2017, 7, 8; doi:10.3390/jlpea7020008.
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