Area-Optimized, Credit-Based, Flow Control Buffered NoC Router
Keywords:
FPGA, FPSoc, MLPR, NoC, PPA, SoCAbstract
The growing popularity of interconnect schemes based on Network-on-Chip (NoC) arises from their exceptional adaptability and scalability. Routers play a significant role in the realm of NoCs, exerting a high impact on performance and cost considerations. To address challenges and enhance the design of NoC routers, the incorporation of numerous innovative techniques becomes essential. We introduce an innovative concept for a NoC router with multiple local ports, developed using Verilog models. Our primary goals encompass the reduction of router size and the enhancement of data transmission speed. The proposed architecture uses XY routing and is further enhanced by optimized buffering, Credit-Based Flow Control, and a Deterministic Clock Approach. The proposed routers are subjected to comprehensive evaluations, scrutinizing their area requirements and operating frequencies. By harnessing distributed control mechanisms, these routers are empowered to operate autonomously, shedding the complexities of intricate handshakes. This, in turn, elevates their overall efficiency and scalability, marking an exceptional breakthrough. The Multi-Local Router design boasts the ability to simultaneously handle multiple independent requests, making it adaptable to high volumes of data traffic in intricate FPSoCs. Its proficiency in meeting essential design criteria such as Power, Performance, and Area (PPA) is truly commendable. To substantiate our claims, we realized and synthesized the proposed router design on a Xilinx Virtex 4 FPGA (4vsx25ff668-12), unequivocally demonstrating its viability and efficacy. This remarkable innovation now opens the door for the implementation of highly efficient NoCs in FPSoCs, particularly for various computationally intensive applications.
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