‘Power-Aware-Test: Methodology for Test Power Analysis and Reduction’


  • Manjunatha Visweswaraiah Research Scholar. Dept of ECE, SJBIT. Bengaluru
  • Somashekar K. Professor, Dept of ECE, SJBIT, Bengaluru


Power-Aware-Test, Semiconductor testing, Design-for-Testability (DFT), Multibit mapping, ATPG (Automatic Test Pattern Generation), Scan architecture, Dynamic power, Multibit reordering, Q-gating, Test power reduction, EDA (Electronic Design Automation)


Facilitating testability in design is pivotal in the integrated circuit design cycle, incorporating logic to facilitate comprehensive defect testing during manufacturing. However, this addition introduces challenges, particularly regarding power requirements during testing. The consideration of power aspects in the design cycle is crucial, as instances exist where chip failures attributed to power issues during testing have adversely impacted overall yield. Balancing the imperative for thorough testing with the potential power-related pitfalls is integral to ensuring the reliability and success of the integrated circuit in the manufacturing process.


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How to Cite

Visweswaraiah, M. ., & K., S. . (2024). ‘Power-Aware-Test: Methodology for Test Power Analysis and Reduction’. International Journal of Intelligent Systems and Applications in Engineering, 12(14s), 498–504. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/4686



Research Article