Design and Implementation of High Speed, Low Power LVDS Receiver Architecture in 18nm FINFET Process Technology
Keywords:LVDS, TIA/EIA-644, Receiver, Low power, High speed, FinFET
The Proposed work offers a novel LVDS (low-voltage differential signalling) receiver circuit design and implementation that is full adherence to the LVDS specification. The architecture is proposed to satisfy the needs of applications which requires fast data speeds and minimal power usage. This LVDS receiver architecture composed of Common mode compressor stage, amplification stage, Differential to Single Ended (D2S) and Buffer stages. The LVDS receiver Circuit simulations show that the receiver supports 5 Gbps data rate, 0.67 mA current at 0-2.4V input supply. With a power consumption of 1.2mW, the circuit aims to provide low power consumption and high data rate. The suggested circuit efficiency and validity are confirmed by achieving circuit simulation in 18 nm FinFET standard technology at 1.8V I/O (Input/Output interface) voltage. The LVDS has the benefit of supporting both low power and high-speed signalling. Furthermore, it is free from the severe under and overshoots that are a feature of high-speed rail-to-rail signalling standards. With greater input supply voltage ranges of 0 to 2.4 volts, this design is easily transportable to multiple application with different voltage levels. The proposed design exhibits rising-falling delays, P2P (Peak to Peak) rise-fall jitter in the transient simulation, also shows Gain in AC simulation results. The P2P Rise and fall jitter tabulated from Eye diagrams representation of output waveform for Typical, Slow, and Fast corners measured at different temperatures with respect common mode voltage range. Through AC modelling, a gain of 7.67dB is obtained at typical corner level with input voltage of 1.2V. For the suggested LVDS receiver architecture, additionally rise, fall delay characteristics were captured by Monte Carlo simulations for various common mode voltage ranges like 100 mV, 1.2V, and 2.3V. The layout of proposed LVDS architecture is designed by using desired layout techniques to achieve area optimization. Hence designed proposed LVDS receiver architecture supports the total area of 49μm*76μm.
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