Design and Implementation of High Speed, Low Power LVDS Receiver Architecture in 18nm FINFET Process Technology


  • Nanditha M. S. Research Scholar, VTU, Belagavi, Karnataka ,590018, India, Research Centre, Bangalore Institute of Technology (BIT), Bangalore, Karnataka 560004, India.
  • Vijaya Prakash A. M. Dept of ECE, Bangalore Institute of Technology (BIT), Bangalore, Karnataka 560004, India


LVDS, TIA/EIA-644, Receiver, Low power, High speed, FinFET


The Proposed work offers a novel LVDS (low-voltage differential signalling) receiver circuit design and implementation that is full adherence to the LVDS specification. The architecture is proposed to satisfy the needs of applications which requires fast data speeds and minimal power usage. This LVDS receiver architecture composed of Common mode compressor stage, amplification stage, Differential to Single Ended (D2S) and Buffer stages. The LVDS receiver Circuit simulations show that the receiver supports 5 Gbps data rate, 0.67 mA current at 0-2.4V input supply. With a power consumption of 1.2mW, the circuit aims to provide low power consumption and high data rate. The suggested circuit efficiency and validity are confirmed by achieving circuit simulation in 18 nm FinFET standard technology at 1.8V I/O (Input/Output interface) voltage. The LVDS has the benefit of supporting both low power and high-speed signalling. Furthermore, it is free from the severe under and overshoots that are a feature of high-speed rail-to-rail signalling standards. With greater input supply voltage ranges of 0 to 2.4 volts, this design is easily transportable to multiple application with different voltage levels. The proposed design exhibits rising-falling delays, P2P (Peak to Peak) rise-fall jitter in the transient simulation, also shows Gain in AC simulation results. The P2P Rise and fall jitter tabulated from Eye diagrams representation of output waveform for Typical, Slow, and Fast corners measured at different temperatures with respect common mode voltage range. Through AC modelling, a gain of 7.67dB is obtained at typical corner level with input voltage of 1.2V. For the suggested LVDS receiver architecture, additionally rise, fall delay characteristics were captured by Monte Carlo simulations for various common mode voltage ranges like 100 mV, 1.2V, and 2.3V. The layout of proposed LVDS architecture is designed by using desired layout techniques to achieve area optimization. Hence designed proposed LVDS receiver architecture supports the total area of 49μm*76μm.


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Yumei Diao, Xingyuan Tong School of Electronics Engineering, Xi'an University of Posts and Telecommunications Xi'an, China “Design of Self-Biased LVDS Receiver for DAC in High-Speed DDS Systems” IEEE 2nd International Conference on Electronics and Communication Engineering (ICECE),2019.

Bincy P Chacko, Christo Ananth, Francis Xavier Engineering College Tirunelveli, Tamil Nadu” Analysis and Design of Low Voltage Low Noise LVDS Receiver” IOSR Journal of Electronics and Communication Engineering 2014.

Wei Fan, Zhelu Li, Jianxiong Xi, Lenian He, Kexu Sun, Ning Xie “A 1.2 Gbps Failsafe Low Jitter LVDS Transmitter Receiver Applied in CMOS Image Sensor”7th International Conference on Modern Circuits and Systems Technologies ,2018.

Gianluca Traversi, Francesco De Canio, Valentino Liberali and Alberto Stabile INFN Pavia, Italy Universita degli Studi di Milano, Italy” Design of LVDS Driver and Receiver in 28 nm CMOS Technology for Associative Memories” 6th MOCAST, 2017.

Sultan A. Alqarni, Ahmed K. Kamal National Center for Electronics and Photonics, King Abdulaziz City for Science and Technology (KACST), Riyadh, Kingdom of Saudi Arabia “LVDS Receiver with 7mW Consumption at 1.5 Gbps,” 26th International Conference on Microelectronics (ICM), 2014.

Niraj Kumar Jha, Dishank Yadav, Anuj Maheshwari, Mrigank Sharad, IIT Kharagpur, West Bengal, IN” Radiation Hardened High-Speed LVDS compliant Transceiver” CONIELECOMP,2019.

Seong Siong, Lee, Lini Lee, Fabian Wai Lee Kung, Ahmed Saad, Harikrishnan Ramiah, Gim Heng Tan, Malaysia” A Low Power High Precision Trim-less Envelope Detector for Fail-Safe Circuit in LVDS Receiver”, IEEE Transactions on Circuits and Systems II,2020

Liang Xie, Shunle Guo, Zhaoxi Li, Xiangtan Jin, School of Physics and Electronics, Hunan Normal University, Changsha, China” A High-Speed Rail-to-Rail Operational Amplifier with Constant-gm for LVDS Receiver” IEEE 20th International Conference on Communication Technology (ICCT), 2020.

G. A. Matig-a, M. R. Yuce and J. Redouté, "An Integrated LVDS Transmitter–Receiver System with Increased Self-Immunity to EMI in 0.18-µm CMOS," IEEE Transactions on Electromagnetic Compatibility, 2016.

P. Vijaya Sankara Rao, Nachiket Desai, Pradip Mandal, Indian Institute of Technology Kharagpur” A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination” Circuits Syst Signal Process ,2012.

B.Faes, J.Christiansen, P. Moreira, P. Reynaert, P. Leroux, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven Belgium “A 2.56 Gbps Radiation Hardened LVDS/SLVS Receiver in 65 nm CMOS,” AMICSA, 2016.

Xu Bai, Jianzhong Zhao, Shi Zuo, Yumei Zhou, Institute of Microelectronics of Chinses Academy of Science, Beijing China, “A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology” MDPI Journal, electronics,2019.

Hanyang Xua, Jian Wang, Jinmei Laib, ASIC and System State Key Laboratory, Fudan University, Shanghai, China “Design of a power efficient self-adaptive LVDS driver.” IEICE Electronics Express ,2018.

Graceffe, G.A. Gatti, U. Calligaro, C, RedCat Devices, Milan, Italy “A 400 Mbps radiation hardened by design LVDS compliant driver and receiver.” ICECS,2016

Hung-Wen Lin, Tzu-Hao Lin, Yuan Ze University Chung-Li City, Taiwan” A 0.3V, 625Mbps LVDS Driver in 0.18um CMOS Technology” IEEE International Conference on Semiconductor Electronics (ICSE),2020.




How to Cite

M. S., N. ., & A. M., V. P. . (2024). Design and Implementation of High Speed, Low Power LVDS Receiver Architecture in 18nm FINFET Process Technology. International Journal of Intelligent Systems and Applications in Engineering, 12(15s), 229–239. Retrieved from



Research Article