Efficient Design of Configurable Logic Block with Customized LUT using Reversible Fault Tolerant Gates
Keywords:
Look-Up Table, FPGA, Fault Tolerant, Reversible Logic, Low Power Dissipation, Garbage OutputAbstract
The parity of the input vector must match the parity of the output vector in a fault-tolerant reversible logic gate circuit. It enables the circuit's problem to be discovered. As a result, parity-preserving reversible logic will assist in the development of fault-tolerant systems for nanotechnology. It is commonly recognized that fault-tolerant (FT) reversible logic gates (RLG) are compatible with revolutionary computing paradigms such as optical and quantum computing. We presented reversible fault-tolerant lookup tables (LUTs) in this paper, which are employed in the development of Configurable logic blocks (CLB). CLB architecture employs fault-tolerant reversible logic components such as D-Latch, MS-Flip-flop, and Multiplexer. The suggested architecture is simulated, tested logically, and implemented using an FPGA Spartan 3. The simulation findings and implementation demonstrate the reversible fault tolerant gate design's functioning. The power dissipation and delay in reversible fault tolerant gates are found to be less, with a power reduction of around 95.5 % at 90 nm CLB technology.
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