Low Power and High throughput Reconfigurable FIR Filter Architecture using RRNS for SDR Applications

Authors

  • Manjunath P. S. Assistant Professor, Dept. of ETE, BMSCE,
  • Sapna Kumari C. Department of ECE, Nitte Meenakshi institute of technology, Bangalore
  • Rajashekhar U. Government Engineering College, Huvinahadagali - 583219
  • Thirthe Gowda M. T. Department of Computer Science and Engineering, Government Engineering College, Hassan, Karnataka, India
  • Sharath S. Government Engineering College, Chamarajanagar, Visvesvaraya Technological University, Belgaum

Keywords:

Reconfigurable FIR filter, Redundant-RNS, Parallel Prefix Adder, QRNS, FPGA

Abstract

A RNS significant RNS (Residue Number System) FIR filter design for Software Defined Radio (SDR) filtration is proposed, with the properties to satisfy such as clustering and concurrency process, this system provides a remarkable performance for the FIR filters. The proposed method is a novel technique for the minimization of the various time delaying parameters with the operation of the Distribution Arithmetic (DA) based residue processing. The proposed FIR filter with core optimized RNS has the benefit of rising performance, lowering processing latency delay with the suitable utilization of the existing RAM blocks on the FPGA, with the simulation results it can be observed that filter size with its operation are channelized and corresponding decrease in the operation logic with FPGA which can be considered as the cost effective as well. One of the major advantage of the proposed system as it can be noted that performance is improved comparatively, the operations which are to be done by the similar experimental setup requires more than 8 taps and 64 tap requires higher order hardware’s.  The cost effective and high throughput Finite Impulse Response (FIR) Filter is proposed using Reconfigurable Residue Number System (RRNS). The new design proposed here the same benefits as that of, add and shift method used before. The complexity of the system is reduced whenever the RRNS system has been added. The Vivado Design Suite & Artix-7 are used to implement the logical structure created. Inducer complete exercise 64-Tap filter is designed. The binary added is used to replace the classical modulo added. This will enhance the accuracy produced by single modulo reduction stage. The area is reduced by approximately 18%. In comparison with the multiplier in each tap with two's complement filter, the index based arithmetic multifaceted filter diminishes the Quadratic RNS off about a 69%. The newly designed filter requires only 45% of LE when compared to the traditional design.

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Published

24.03.2024

How to Cite

P. S., M. ., Kumari C., S. ., U., R. ., M. T., T. G. ., & S., S. . (2024). Low Power and High throughput Reconfigurable FIR Filter Architecture using RRNS for SDR Applications. International Journal of Intelligent Systems and Applications in Engineering, 12(18s), 99–110. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/4955

Issue

Vol. 12 No. 18s (2024)

Section

Research Article

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