Comparative Analysis of FPGA with Network on Chip Architecture with Routing Techniques

Authors

  • E. G. Satish Assistant Professor, Department of Computer Science and Engineering, Nitte Meenakshi Institute of Technology, Bangalore, India
  • Rajeshwari S. B. Assistant Professor, Department of Information Science and Engineering, M S Ramaiah Institute of Technology, Bangalore, India
  • Vinay T. R. Assistant Professor, Department of Artificial Intelligence and Data Science, M S Ramaiah Institute of Technology, Bangalore, India
  • Asmathunnisa N. Research Scholar, Department of Computer Science and Engineering, M S Ramaiah Institute of Technology, Bangalore, India and affiliated to Visvesvaraya Technological University, Belagavi, Karnataka, India
  • Kalpitha S. Naik Undergraduate Student, Department of Artificial Intelligence and Machine Learning, M S Ramaiah Institute of Technology, Bangalore, India
  • Jagadish S. Kallimani Professor and Head, Department of Artificial Intelligence and Machine Learning, M S Ramaiah Institute of Technology, Bangalore, India

Keywords:

Run-Time Reconfiguration (RTR), Field programmable gateway array FPGA, Network on Chip, Reprogrammable Computing RC, programmable active memories PAM

Abstract

The reprogrammable device architectures may bring one-of-a-kind computational abilities to play out the different undertakings. It will help to execution and vitality effectiveness of equipment utilities with the adaptability of software programming and hardware components In a few areas, they are the best way to accomplish the required, constant execution without manufacturing specially coordinated Integrated Circuits (IC). The IC’s usefulness will be fixed and updated amid their operational IC lifecycle for a specific task required. The field of reprogrammable computing device architectures provides a guide to excel information to the body of knowledge Collected in computing architecture and technology, run-time reconfiguration, tools, and applications. The essential focal points of run-time reconfiguration in gadgets are lessened power utilization, equipment reuse, and adaptability.

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References

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Published

24.03.2024

How to Cite

Satish, E. G. ., S. B., R. ., T. R., V. ., N., A. ., S. Naik, K. ., & Kallimani, J. S. . (2024). Comparative Analysis of FPGA with Network on Chip Architecture with Routing Techniques. International Journal of Intelligent Systems and Applications in Engineering, 12(19s), 471–478. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/5087

Issue

Vol. 12 No. 19s (2024)

Section

Research Article

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