An High Speed FPGA Implementation of Image Contrast Enhancement using Histogram Equalisation
Keywords:
Contrast enhancement, FPGA, HE, High speed, Pipelined ArchitectureAbstract
Image enhancement is one of the basic and important image processing techniques used to improve the quality of image in wide variety of applications including real-time video surveillance, medical imaging, industrial automation, intelligent self navigation systems, and oceanography. This research paper proposes a novel high-speed parallel and pipelined reconfigurable field programmable gate arrays (FPGA) architecture for histogram equalisation to enhance the contrast of an image. The proposed parallel histogram equalisation architecture comprises of comparators, unique counter modules and a register array. The proposed architecture has been developed using register transfer level (RTL) - compliant Verilog HDL code, simulated using Xilinx’s integrated simulator (ISim), synthesized and implemented on a Kintex7 family of FPGA device. Simulation and synthesis results demonstrate that the proposed architecture can be implemented with a processing time of 2.364ns with a maximum frequency of operation 422.976MHz. Extremely dark images and overexposed images from standard datasets have been used to test the performance of the developed architecture and compared with matlab results through the quality metrics like Entropy, Contrast per pixel. Results obtained by proposed architecture and the results obtained by matlab found similar. Experimental results show that the proposed architecture outperforms other existing architectures.
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