A Low-Latency, Area-Efficient Convolution Network for FPGA Acceleration
Keywords:
EffiConvNet, Area Efficient, Low Latency, FPGAAbstract
The goal of the technology known as Field Programmable Gate Arrays (FPGA) is to improve the safety, performance, and efficiency of cryptographic operations in contexts with limited resources. The use of deep learning has been more important in recent years, particularly with regard to the achievement of low latency and space efficiency in FPGA-based implementations. This study paper gives According to the suggested model, which is called EffiConvNet (Efficient Convolution Network), ternary neural networks, logic expansion, and block convolution are all integrated. Block Convolution is a technique that tries to optimise the data dependence among the spatial tiles. This helps to ease the load on chip memory and facilitates efficient processing. In order to do this, logic expansion is used, which replaces the XNOR gates with neural networks. This allows for more effective utilisation of resources. In order to achieve the desired degree of efficiency at the training stage, further ternary neural networks are used. The experimental results of our technique on real-world tasks reveal that it is successful. Furthermore, these coupled architectures together (EffiConvNet) illustrate the efficacy of our approach. While assuring optimal resource utilisation and better inference performance, the combination strategy that has been described offers a potential option for addressing the obstacles that are connected with the deployment of large-scale neural networks on FPGAs.
Downloads
References
P. Dhilleswararao, S. Boppu, M. S. Manikandan and L. R. Cenkeramaddi, "Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey," in IEEE Access, vol. 10, pp. 131788-131828, 2022, doi: 10.1109/ACCESS.2022.3229767.
R. Sayed, H. Azmi, H. Shawkey, A. H. Khalil and M. Refky, "A Systematic Literature Review on Binary Neural Networks," in IEEE Access, vol. 11, pp. 27546-27578, 2023, doi: 10.1109/ACCESS.2023.3258360
K. S. Zaman, M. B. I. Reaz, S. H. Md Ali, A. A. A. Bakar and M. E. H. Chowdhury, "Custom Hardware Architectures for Deep Learning on Portable Devices: A Review," in IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 11, pp. 6068-6088, Nov. 2022, doi: 10.1109/TNNLS.2021.3082304
R. Zhao, W. Song, W. Zhang, T. Xing, J.-H. Lin, M. Srivastava, R. Gupta, and Z. Zhang, ‘‘Accelerating binarized convolutional neural networks with software-programmable FPGAs,’’ in Proc. ACM/SIGDA Int. Symp. FieldProgram. Gate Arrays, Feb. 2017, pp. 15–24
K. Javeed, A. El-Moursy and D. Gregg, "EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor," in IEEE Access, vol. 11, pp. 56649-56662, 2023, doi: 10.1109/ACCESS.2023.3282781
Y. Kuang et al., "ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 11, pp. 1631-1641, Nov. 2022, doi: 10.1109/TVLSI.2022.3183126.
L. Guerra, B. Zhuang, I. Reid, and T. Drummond, ‘‘Automatic pruning for quantized neural networks,’’ 2020, arXiv:2002.00523.
G. Anderson and C. P. Berg, ‘‘The high-dimensional geometry of binary neural networks,’’ 2017, arXiv:1705.07199.
T. Fujii, S. Sato, and H. Nakahara, ‘‘A threshold neuron pruning for a binarized deep neural network on an FPGA,’’ IEICE Trans. Inf. Syst., vol. 101, no. 2, pp. 376–386, 2018.
Y. Xu, X. Dong, Y. Li, and H. Su, ‘‘A Main/Subsidiary network framework for simplifying binary neural networks,’’ in Proc. IEEE/CVF Conf. Comput. Vis. Pattern Recognit. (CVPR), Jun. 2019, pp. 7154–7162.
X. Xiao and Z. Wang, ‘‘AutoPrune: Automatic network pruning by regularizing auxiliary parameters,’’ in Proc. Adv. Neural Inf. Process. Syst., vol. 32, Dec. 2019, pp. 1–15
Y. Li and F. Ren, ‘‘BNN pruning: Pruning binary neural network guided by weight flipping frequency,’’ in Proc. 21st Int. Symp. Quality Electron. Design (ISQED), Mar. 2020, pp. 306–311.
T. Geng, A. Li, T. Wang, C. Wu, Y. Li, R. Shi, W. Wu, and M. Herbordt, ‘‘O3BNN-R: An out-of- order architecture for high-performance and regularized BNN inference,’’ IEEE Trans. Parallel Distrib. Syst., vol. 32, no. 1, pp. 199–213, Jan. 2021.
J. Gao, Q. Liu, and J. Lai, ‘‘An approach of binary neural network energyefficient implementation,’’ Electronics, vol. 10, no. 15, p. 1830, Jul. 2021
Q. Wu, X. Lu, S. Xue, C. Wang, X. Wu, and J. Fan, ‘‘SBNN: Slimming binarized neural network,’’ Neurocomputing, vol. 401, pp. 113–122, Aug. 2020.
B. -K. Yan and S. -J. Ruan, "Area Efficient Compression for Floating-Point Feature Maps in Convolutional Neural Network Accelerators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 2, pp. 746-750, Feb. 2023, doi: 10.1109/TCSII.2022.3213847.
S. Wiedemann et al., "FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons," in IEEE Open Journal of Circuits and Systems, vol. 2, pp. 407-419, 2021, doi: 10.1109/OJCAS.2021.3083332.
J. Wu et al., "An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi- Core Architecture With Transposable Memory and On-Chip Learning," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 11, no. 4, pp. 725-738, Dec. 2021, doi: 10.1109/JETCAS.2021.3114396.
S. Liu, H. Fan, M. Ferianc, X. Niu, H. Shi and W. Luk, "Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs," in IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 8, pp. 3974-3987, Aug. 2022, doi: 10.1109/TNNLS.2021.3055240.
P. Plagwitz, F. Hannig, M. Ströbel, C. Strohmeyer, and J. Teich, ‘‘A safari through FPGA-based neural network compilation and design automation flows,’’ in Proc. IEEE 29th Annu. Int. Symp. Field-Program. Custom Comput. Mach. (FCCM), May 2021, pp. 10–19.
M. Blott, N. J. Fraser, G. Gambardella, L. Halder, J. Kath, Z. Neveu, Y. Umuroglu, A. Vasilciuc, M. Leeser, and L. Doyle, ‘‘Evaluation of optimized CNNs on heterogeneous accelerators using a novel benchmarking approach,’’ IEEE Trans. Comput., vol. 70, no. 10, pp. 1654–1669, Oct. 2021
B. Jacob, S. Kligys, B. Chen, M. Zhu, M. Tang, A. Howard, H. Adam, and D. Kalenichenko, ‘‘Quantization and training of neural networks for efficient integer-arithmetic-only inference,’’ in Proc. IEEE/CVF Conf. Comput. Vis. Pattern Recognit., Jun. 2018, pp. 2704–2713. Y. Lecun. MNIST Datset. [Online]. Available: http://yann.lecun.com/exdb/mnist/
A. Krizhevsky. CIFAR-10 Dataset. [Online]. Available: https://www.cs. toronto.edu/~kriz/cifar.html
Z. Wu, S. Song, A. Khosla, F. Yu, L. Zhang, X. Tang, and J. Xiao. 3d shapenets: A deep representation for volumetric shapes. In 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pages 1912–1920, 2015
M. Ghasemzadeh, M. Samragh, and F. Koushanfar, ``ReBNet: Residual binarized neural network,'' in Proc. IEEE 26th Annu. Int. Symp. Field- Program. Custom Comput. Mach. (FCCM), Apr. 2018, pp. 57_64.
S. Liang, S. Yin, L. Liu, W. Luk, and S. Wei, ``FP-BNN: Binarized neural network on FPGA,'' Neurocomputing, vol. 275, pp. 10721086, Jan. 2018.
Xilinx Research Labs. (2017). BNN-PYNQ. [Online]. Available: https://github.com/Xilinx/BNN-PYNQ.
M. Blott, T. B. Preuÿer, N. J. Fraser, G. Gambardella, K. O'brien, Y. Umuroglu, M. Leeser, and K. Vissers, ``FINN-R: An end-to-end deeplearning framework for fast exploration of quantized neural networks,'' ACM Trans. Recongurable Technol. Syst., vol. 11, no. 3, pp. 1-23,Sep. 2018.
Y. Umuroglu, N. J. Fraser, G. Gambardella, M. Blott, P. Leong, M. Jahre, and K. Vissers, ``FINN: A framework for fast, scalable binarized neural network inference,'' in Proc. ACM/SIGDA Int. Symp. Field-Program. Gate Arrays, Feb. 2017, pp. 6574.
M. Ghasemzadeh, M. Samragh, and F. Koushanfar, ``ReBNet: Residual binarized neural network,'' in Proc. IEEE 26th Annu. Int. Symp. Field-Program. Custom Comput. Mach. (FCCM), Apr. 2018, pp. 5764.
P. Guo, H. Ma, R. Chen, P. Li, S. Xie, and D.Wang, ``FBNA: A fully binarized neural network accelerator,'' in Proc. 28th Int. Conf. Field Program. Log. Appl. (FPL), Aug. 2018, pp. 511513.
J. Kim, J. K. Lee, and K. M. Lee, “Accurate image super-resolution using very deep convolutional networks,” in Proc. IEEE Conf. Comput. Vis. Pattern Recognit., 2016, pp. 1646–1654.
N. Suda et al., “Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks,” in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, 2016, pp. 16–25.
Y. S. Shao et al., “SIMBA: Scaling deep-learning inference with multichip- module-based architecture,” in Proc. 52nd Annu. IEEE/ACM Int. Symp. Microarchit., 2019, pp. 14–27.
Y. Ma, Y. Cao, S. Vrudhula, and J.-S. Seo, “Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks,” in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, 2017, pp. 45–54.
V. Maruthi Prasad, B. Bharathi, "A Novel Trust Negotiation Protocol for Analysing and Approving IoT Edge Computing Devices Using Machine Learning Algorithm", International Journal of Computer Networks and Applications (IJCNA), 9(6), PP: 712-723, 2022, DOI: 10.22247/ijcna/2022/217704.
Prasad, V. M. ., & Bharathi, B. (2023). Security in 5G Networks: A Systematic Analysis of High-Speed Data Connections. International Journal on Recent and Innovation Trends in Computing and Communication,11(5),216–222. https://doi.org/10.17762/ijritcc.v11i5.6608
Downloads
Published
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.
All papers should be submitted electronically. All submitted manuscripts must be original work that is not under submission at another journal or under consideration for publication in another form, such as a monograph or chapter of a book. Authors of submitted papers are obligated not to submit their paper for publication elsewhere until an editorial decision is rendered on their submission. Further, authors of accepted papers are prohibited from publishing the results in other publications that appear before the paper is published in the Journal unless they receive approval for doing so from the Editor-In-Chief.
IJISAE open access articles are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License. This license lets the audience to give appropriate credit, provide a link to the license, and indicate if changes were made and if they remix, transform, or build upon the material, they must distribute contributions under the same license as the original.
