A Novel Zipper Logic Based Hybrid 1-Bit Full Adder Circuit Design
Keywords:
Complementary Metal-Oxide-Semiconductor (CMOS) Logic, Hybrid Circuit Design, Performance Evaluation., Zipper Logic, 1-bit Full AdderAbstract
Zipper logic is a design that integrates many logic types or approaches to create an efficient and optimal circuit. A 1-bit Full Adder (FA) is a basic building block in digital circuits that adds two 1-bit binary inputs (A and B) plus a Carry Input (Cin) to create a sum output (S) and a Carry Output (Cout). This study examined the concept of a zipper logic-based hybrid 1-bit FA circuit design, which pertains to a particular method of designing a digital circuit that performs the addition operation on two 1-bit binary integers (bits). The performance parameters of the hybrid circuit are assessed and compared to standard 1-bit FA designs, revealing considerable improvements in latency and energy usage. The suggested FA cell's performance has been analyzed using a Cadence simulator at the 16 nm production node, where it was compared to that of existing FAs throughout a supply voltage spectrum of 0.4 to 1.0 V. When compared to the other adder, the suggested adder improved Average Power Consumption (ADP) by 48.9% and Power Delay Product (PDP) by 66.7% when conducting at 0.8V.
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