Implementation of Reconfigurable Modified Advanced Encryption Algorithm with Area Optimization
Keywords:
Advanced Encryption System, Galois field, Mix column, key expansion, Area Optimization, IOT applicationAbstract
With the rise of computer technology and the Internet in the era of IoT and Industry 4.0, ensuring information security has become paramount. The Advanced Encryption Standard (AES) has emerged as a leading cryptography standard, garnering significant attention from hardware designers. IOT end devices requires low power and fast processing hence modification in AES is needed. This paper presents a novel implementation of AES, focusing on minimizing hardware area. Utilizing Vivado 2015.4, we conduct simulations and compare results, exploring coding methodologies. Our design demonstrates superior resource efficiency compared to others, addressing the critical need for secure communication in modern interconnected systems. The papers also showcases the various methods that can further increase the effectiveness and minimizes the area utilization.
Downloads
References
Rady, Ahmed, Ehab EL Sehely, and AM EL Hennawy. "Design and implementation of area optimized AES algorithm on reconfigurable FPGA." In 2007 Internatonal Conference on Microelectronics, pp. 35-38. IEEE, 2007.
Standaert, Francois-Xavier, Gaël Rouvroy, Jean-Jacques Quisquater, and Jean-Didier Legat. "Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs." In Cryptographic Hardware and Embedded Systems-CHES 2003: 5th International Workshop, Cologne, Germany, September 8–10, 2003. Proceedings 5, pp. 334-350. Springer Berlin Heidelberg, 2003.
Mulani, Altaf O., and Pradeep B. Mane. "High-Speed area-efficient implementation of AES algorithm on reconfigurable platform." Computer and Network Security 119 (2019).
Wang, Zhu, Yan Yao, Xiaojun Tong, Qinghua Luo, and Xiangyu Chen. "Dynamically reconfigurable encryption and decryption system design for the internet of things information security." Sensors 19, no. 1 (2019): 143.
Zhang, Xinmiao, and Keshab K. Parhi. "Implementation approaches for the advanced encryption standard algorithm." IEEE Circuits and systems Magazine 2, no. 4 (2002): 24-46.
Gandh, D. Rahul, V. Kamalakannan, R. Balamurugan, and S. Tamilselvan. "FPGA implementation of enhanced key expansion algorithm for Advanced Encryption Standard." In 2014 International Conference on Contemporary Computing and Informatics (IC3I), pp. 409-413. IEEE, 2014.
Alkamil, Arkan, and Darshika G. Perera. "Towards dynamic and partial reconfigurable hardware architectures for cryptographic algorithms on embedded devices." IEEE Access 8 (2020): 221720-221742.
Granado-Criado, Jose M., Miguel A. Vega-Rodríguez, Juan M. Sánchez-Pérez, and Juan A. Gómez-Pulido. "A new methodology to implement the AES algorithm using partial and dynamic reconfiguration." Integration 43, no. 1 (2010): 72-80.
Masoumi, Massoud. "A highly efficient and secure hardware implementation of the advanced encryption standard." Journal of Information Security and Applications 48 (2019): 102371.
Jamuna, S., P. Dinesha, K. PShashikala, and Kumar K. Kishore. "Design and Implementation of Runtime Reconfigurable Encryption Algorithms using Custom ICAP Processor." International Journal of Computer Network and Information Security 11, no. 12 (2019): 10-16.
Chowdhury, A.R., Mahmud, J., Kamal, A.R.M. and Hamid, M.A., 2018, March. MAES: Modified advanced encryption standard for resource constraint environments. In 2018 IEEE Sensors Applications Symposium (SAS) (pp. 1-6). IEEE.
Mane, P. B., and A. O. Mulani. "High speed area efficient FPGA implementation of AES algorithm." International Journal of Reconfigurable and Embedded Systems 7, no. 3 (2018): 157-165.
Sireesha, K., and S. R. Madhava. "A novel approach of area optimized and pipelined FPGA implementation of AES encryption and decryption." International Journal Scientific and Research Publications 3, no. 9 (2013): 1-5.
Fathy, Ahmed, Ibrahim F. Tarrad, Hesham FA Hamed, and Ali Ismail Awad. "Advanced encryption standard algorithm: Issues and implementation aspects." In Advanced Machine Learning Technologies and Applications: First International Conference, AMLTA 2012, Cairo, Egypt, December 8-10, 2012. Proceedings 1, pp. 516-523. Springer Berlin Heidelberg, 2012.
Rajasekar, P., and H. Mangalam. "Design and implementation of power and area optimized AES architecture on FPGA for IoT application." Circuit World 47, no. 2 (2020): 153-163.
Standaert, François-Xavier, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater, and Jean-Didier Legat. "ICEBERG: An involutional cipher efficient for block encryption in reconfigurable hardware." In Fast Software Encryption: 11th International Workshop, FSE 2004, Delhi, India, February 5-7, 2004. Revised Papers 11, pp. 279-298. Springer Berlin Heidelberg, 2004.
Downloads
Published
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.
All papers should be submitted electronically. All submitted manuscripts must be original work that is not under submission at another journal or under consideration for publication in another form, such as a monograph or chapter of a book. Authors of submitted papers are obligated not to submit their paper for publication elsewhere until an editorial decision is rendered on their submission. Further, authors of accepted papers are prohibited from publishing the results in other publications that appear before the paper is published in the Journal unless they receive approval for doing so from the Editor-In-Chief.
IJISAE open access articles are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License. This license lets the audience to give appropriate credit, provide a link to the license, and indicate if changes were made and if they remix, transform, or build upon the material, they must distribute contributions under the same license as the original.
