Implementation of Low Speed Dynamic Comparator with Double Tail Cascode Cross-Coupled Pair to Enhance Gain
Keywords:
low-noise, Comparator, low-power, double tail latch-type comparator.Abstract
The dynamic comparator with low performance is designed with a 28 nm CMOS process with a supply voltage of 1.1 V, and is compared to a wide range of double-tail comparator for power consumption and RMS noise with input. Adding a cross-coupling device to I/P differential couple prevents the internal comparison node from being completely unloaded, as opposed to traditional architectures. This reduces power consumption and achieves similar noise levels at the same time. Measurements show that the proposed comparator achieves an input noise of 230 µV. that suppress power reductions by 50%. The proposed circuit consumes 0.198pJ energy per comparison.
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