Implementation of Digital Low Dropout Voltage Regulators with low ESR and PSRR
Keywords:
ESR, PSSR, Transient Response low dropout regulator (LDO).Abstract
The design of a Digital Low Dropout Voltage Regulators (DLDO) with output voltage is 1.5 V. The load current is in the range of 8 µA to 2 mA with 9% error. The balance of the resistors is an important element in the design of many LDOs, must be taken into account and the ESR tolerances must be determined. The regulator is stabilized with a 1µF output capacitor with 20% tolerance. The temperature range is between -50°C and 100°C for DLDO. The ability of the controller to reject input voltage fluctuations and noise is called PSRR to achieve the large value. The ESR range specified in the specification is between 10m and 300m. In the input voltage range of 1.7V to 2V, the maximum quiescent current under all conditions should be less than 10 µA.
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