A UVM based Reusable Framework for End-To-End Verification of Power Instruction Set Architecture (ISA) Cores
Keywords:
Power ISA, Open Power, A2I, A2O Universal Verification Method-ology (UVM), Functional verification, Scoreboard, Reference model.Abstract
Power ISA is an open Instruction Set Architecture (ISA) enabling processor innovation through open standard collaboration. Many implementations have been developed, each using different microarchitectures to support standard as well as user-defined extensions. To meet this evolution, there is a need for fast, reusable, and implementation-independent test bases for the early verification of these cores. In this paper, we present a reusable framework for the end-to-end verification of Power ISA cores against the ISA specs using the Universal Verification Methodology (UVM). The proposed UVM environment is highly portable and reconfigurable to fit various architectures with minor modifications. We have implemented a predictor model using a modifiable and implementation-free approach that facilitates the easy addition of user-defined extensions. The environment also uses sequence layering to apply a wide range of complex scenarios and test cases. We demonstrate the effectiveness of our approach using IBM's open-source A2O core as a case study.
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