An Efficient FPGA-Based Dynamic Partial Reconfigurable Implementation
Keywords:
Fault Tolerant System, Generic Controller, Partial Reconfiguration, Triple Modular RedundancyAbstract
Today's system developers can choose from many electronic gadgets. There are simple integrated circuits, programmable microcontrollers, bespoke chips, and more complex logic devices on the market. FPGA technology is famous for rapid prototyping and implementing small-unit systems. They offer high logic density and the ability to readily upgrade established designs to meet new standards or change system function or structure. FPGAs have a shorter design cycle than custom devices and can use low-cost design tools. These benefits reduce FPGA design NRE. Their weakness is radiation [1]. This primarily involves SRAM-based FPGAs, which are in high demand because they have high throughput at a low cost. The design of fault-tolerant systems can reduce the number of errors they experience.
A fault-tolerant FPGA design approach is presented as a proposal in this study. This technique can be utilized in systems with a constrained redundancy area and cannot use excess resources while operational. In order to alleviate some of the issues with the system, we will implement FPGA partial dynamic reconfiguration. This technique's primary focus is recovery from both temporary and permanent flaws. SEU faults will be simulated via errors in the FPGA configuration memory. After the job, an analysis of the solution's hardware overhead and the effectiveness of the secured system design is carried out.
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