FPGA Implementation of Adaptive Hold Logic Vedic Fused Dot Product Floating-Point Multiplier Using Razor Flip -Flop

Authors

  • G. Erna Associate Professor, Department of Electronics and Communication Engineering, PACE Institute of Technology & Sciences (UGC Autonomous) Ongole-523272 Andhra Pradesh, India,
  • V. Saidulu Senior Assistant Professor, Department of Electronics and Communication Engineering, Mahatma Gandhi Institute of Technology, Jawaharlal Nehru Technological University, Hyderabad, India,
  • G. Srihari Associate Professor, School of Technology, The Apollo University, Chittoor
  • K. Babu Rao Professor, Department of Electronics and Communication Engineering, Usha Rama College of Engineering and Technology (UGC Autonomous), Telaprolu, ungutur mandal, krishan District, Andhra Pradesh, India

Keywords:

Vedic Fused Dot Product, NBTI and PBTI, Adaptive Hold Logic, Razor Flip Flop, FPGA, CSA

Abstract

In the recent technology of high-speed digital signal processing system has been increases with the explosive growth in mobile computing and portable multimedia application. In this digital signal processing method of arithmetic operation will have more number of floating point multipliers it will used in FFT and DCT based applications, but it will have more latency and less throughput and also take more area consumptions. Thus, this proposed work introduced to Reduced the latency in floating point multiplication with fused method, therefore here fused method integrated with Vedic multiplier using AHL and Razor flip flop. Here, this proposed work will Designed at 16-bit size in Verilog HDL, and it will Synthesized in Xilinx FPGA S6LX9-2TQG144, and finally compared all the parameters in terms of area, delay and power.

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Published

27.10.2023

How to Cite

Erna, G. ., Saidulu, V. ., Srihari, G. ., & Rao, K. B. . (2023). FPGA Implementation of Adaptive Hold Logic Vedic Fused Dot Product Floating-Point Multiplier Using Razor Flip -Flop. International Journal of Intelligent Systems and Applications in Engineering, 12(2s), 420–434. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/3642

Issue

Vol. 12 No. 2s (2024)

Section

Research Article

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Copyright (c) 2023 G. Erna, V. Saidulu, G. Srihari, K. Babu Rao

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