An Efficient Low-Power Reconfigurable Model For CMOS-Based SRAM Using FPGA
Keywords:
Complementary metal oxide semiconductor (CMOS), static random-access memory (SRAM), field programming gate array (FPGA),, Complex Programmable Logic Devices (CPLDs), Configurable Logic Blocks (CLBs), logical elements (LEs).Abstract
Due to the high-speed communication process in the memory cell, there is a requirement of a high-speed parallel switching operation to enhance the flexibility, reliability and accuracy of the memory cells. To achieve this, a low-power complementary metal oxide semiconductor (CMOS)-based static random-access memory (SRAM) using field programming gate array (FPGA) architecture has been proposed in this paper. High-speed reconfigurable on-chip CMOS SRAM memory blocks are used for optimal utilization of fast and low-power SRAM blocks and have been deployed on the 10T SRAM cells. The proposed method is used to help facilitate fast access to the reconfigurable data bits using Reconfigurable shadow CMOS SRAM Cells. The combined effect of reconfigurable CMOS SRAM cells and shadow SRAM technologies are used to reduce the delay and power by about 8.136 ns and 0.018 W for the 10T SRAM memory cells, as per the simulation result. Due to these phenomena, the area utilization for deployment is higher as compared to conventional methods such as 4T SRAM and 6T SRAM. This has been achieved with the help of FPGA-based CMOS SRAM memory cells.
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