Fusion and Analytical Research of Active Scheduling Procedures Targeting Reconfiguarable Environment

Authors

  • Ashish S. Bhopale Dept. of Electronics and Telecommunication Prof. Ram Meghe Institute of Technology and Research Badnera-Amravati, India
  • Archana O. Vyas Dept. of Electronics and Telecommuinication Engineering Raisoni Centre for Research and Innovation G. H. Raisoni University, Amravati, India

Keywords:

HDL, FPGA, Scheduling Algorithm, Xilinx Vivado, HLS, CPLD

Abstract

In the computing environment, multiple data packets arrive at the node for processing. Multiple tasks are engaged to handle these data packets which accepts these data packets process them and executes further required steps. For handling the multiple data packets simultaneously, multiple tasks are engaged which utilizes the limited resources on time sharing basis. To make the limited resources useful and handle the multiple tasks efficiently, strong, highly active task scheduling algorithm is required. This research paper demonstrates the multiple tasks arriving and getting executed simultaneously in addition to the routing tasks. The algorithm is described using high speed integrated circuit hardware description language. The description is targeted to the modern concurrent programmable hardware architecture. The hardware description is performed using the Xilinx Vivado High Level Synthesis (HLS) Tool.

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Published

30.11.2023

How to Cite

Bhopale, A. S. ., & Vyas, A. O. . (2023). Fusion and Analytical Research of Active Scheduling Procedures Targeting Reconfiguarable Environment. International Journal of Intelligent Systems and Applications in Engineering, 12(6s), 687–693. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/4007

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Research Article