Scheduling Algorithm in Reconfigurable Architecture for Multicore Environment
Keywords:
HDL, FPGA, Scheduling Algorithm, Xilinx Vivado, HLS, CPLDAbstract
Multiple tasks arrive at the node which are processed speedily to attend the data packets arriving from the multiple nodes and hence extend the required services. To handle multiple data packets, multiple tasks are executed at the same time to speed up the process. On the hardware side each node is having limited resources on which multiple tasks uses these hardware resources on time sharing basis. Through this research paper, a new technique for handling the multiple tasks concurrently is disclosed. The proposed technique is implemented using the reconfigurable architecture which is famous for concurrent hardware execution. The algorithm is described using high speed integrated circuit hardware description language. The description is targeted to the modern concurrent programmable hardware architecture. The hardware description is performed using the Xilinx Vivado High Level Synthesis (HLS) Tool.
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