Design of Area and power Efficient MAC architecture using CNN for DSP Applications
Keywords:
ASIC, CNN, HDL, MACAbstract
The planned task aims to develop a highly efficient MAC Architecture utilizing CNN on a Digital Signal Processor through the implementation of Verilog HDL for functional verification, Synthesis, and Physical Design using Cadence Genus and Innovus in the ASIC design flow. This architecture aims to significantly enhance the processor's speed by executing rapid multiplication and addition operations, characteristic of the current MAC unit. With the rapid evolution of technology, digital signal processors have become increasingly potent and resourceful. The cornerstone of this MAC architecture lies in its utilization of CNN, enabling swift operations. Constructing MAC architecture necessitates the integration of various digital blocks within the design. The proposed design achieves an exceptional reduction of 80.13% in both area and power, consequently resulting in a substantial decrease in the architecture's size. Moreover, the proposed design offers the added benefits of optimized power utilization and minimized area requirements.
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