Design of an Error Detection Fault Tolerant Arbiter for a Network on Chip
Keywords:
Route-Controller Network on Chip, System on Chip, FIFO-Buffer, Crossbar switching, route control, ArbiterAbstract
Device to Device communications and System-on-Chip (SoC) communications needs thehigh-speed data transfer with low hardware resource utilization. However, the conventional methods have resulted in higher area, high power consumption including time delay .This paper thus proposes the concept of Fault Tolerant Arbiter based Network on Chip (FTA-NoC)architecture with FIFO-Buffer, crossbar switching, route control, and arbiter modules. This work presents encoder and decoder-based route controlling using fault tolerant arbiter, which was introduced for high speed, error-free route calculation with less hardware resources in NOC.Initially, data generated from the different devices is stored into FIFO-Buffer logic, which allocates the data based on IP addresses. Then, route controller module controls the different routers in crossbar switching, which arecontrolled by priority-based scheduling. The data is then sent from the source to the destination using arbitrator in accordance with request levels. The simulation results show how well the FTA-NOC performs in terms of area, latency, and power when compared to the most advanced NoC architectures.
Downloads
References
Mehmood, Farrukh, et al. "An efficient and cost-effective application mapping for network-on-chip using Andean condor algorithm." Journal of Network and Computer Applications 200 (2022): 103319.
Parepalli, Ramanamma, and Mohan Kumar Naik. "Design alternatives of Network-on-Chip (NoC) Router microarchitecture for future Communication System." 2022 International Conference on Advances in Computing, Communication and Applied Informatics (ACCAI). IEEE, 2022.
Chen, Yuan-Ho, et al. "A VLSI Chip for the Abnormal Heart Beat Detection Using Convolutional Neural Network." Sensors 22.3 (2022): 796.
Manzoor, Misbah, and Roohie Naaz Mir. "PAAD (Partially adaptive and deterministic routing): A Deadlock Free Congestion Aware Hybrid Routing for 2D Mesh Network-on-chips." Microprocessors and Microsystems (2022): 104551.
Sharma, Ashish, et al. "Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture." Microprocessors and Microsystems 91 (2022): 104526.
Gogoi, Ankur, et al. "Application driven routing for mesh based network-on-chip architectures." Integration 84 (2022): 26-36.
Yazdanpanah, Fahimeh, and Raheel Afsharmazayejani. "A systematic analysis of power saving techniques for wireless network-on-chip architectures." Journal of Systems Architecture 126 (2022): 102485.
Jadhav, Nathrao B., and Bharat S. Chaudhari. "Efficient Non-Blocking Optical Router for 3D Optical Network-on-Chip." Optik (2022): 169563.
Biswas, Arnab Kumar. "Using Pattern of On-off Routers and Links and Router Delays to Protect Network-on-Chip Intellectual Property." ACM Transactions on Computer Systems (TOCS) (2022).
Al-Azzwai, Waleed K., Aqeel A. Al-Hilali, and Laith F. Jumma. "Design and implementation 4x4 Network on Chip (NoC) using FPGA." Periodicals of Engineering and Natural Sciences (PEN) 10.3 (2022): 341-349.
Seetharaman, Gopalakrishnan, and Debadatta Pati. "Design and Area Performance Energy Consumption Comparison of Secured Network-on-Chip with PTP and Bus Interconnections." Journal of The Institution of Engineers (India): Series B (2022): 1-13.
Xia, Yuhao, et al. "Strict non-blocking four-port optical router for mesh photonic network-on-chip." Journal of Semiconductors 43.9 (2022): 092301-1.
Velangi, Radha, and S. S. Kerur. "Hardware Implementation and Comparison of OE Routing Algorithm with Extended XY Routing Algorithm for 2D Mesh on Network on Chip." Micro-Electronics and Telecommunication Engineering. Springer, Singapore, 2022. 159-171.
Kashi, Somayeh, et al. "A multi-application approach for synthesizing custom network-on-chips." The Journal of Supercomputing (2022): 1-23.
Florida, L. Mary, S. Brilly Sangeetha, and K. Krishna Prasad. "OPTIMISED META-HEURISTIC QUEUING MODEL IN VLSI PHYSICAL DESIGN."
Amin, Waqar, Fawad Hussain, and Sheraz Anjum. "iHPSA: An improved bio-inspired hybrid optimization algorithm for task mapping in Network on Chip." Microprocessors and Microsystems 90 (2022): 104493.
Fan, Weibei, et al. "Communication and performance evaluation of 3-ary n-cubes onto network-on-chips." Science China Information Sciences 65.7 (2022): 1-3.
Gupta, Ruchika, et al. "Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging." Proceedings of the Great Lakes Symposium on VLSI 2022. 2022.
Kaleem, Muhammad, and Ismail Fauzi Bin Isnin. "Interval Based Transaction Record Keeping Mechanism for Adaptive 3D Network-on-Chip Routing."
F. Imani, Mohammadreza, Sergi Abadal, and Philipp Del Hougne. "Metasurface‐Programmable Wireless Network‐On‐Chip." Advanced Science (2022): 2201458.
Thakkar, Ishan G., et al. "Hardware Security in Emerging Photonic Network-on-Chip Architectures." Emerging Computing: From Devices to Systems. Springer, Singapore, 2023. 291-313.
Bhamidipati, Padmaja, and Avinash Karanth. "HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture." IEEE Transactions on Emerging Topics in Computing 10.2 (2022): 537-548.
Kunthara, Rose George, et al. "DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks." Proceedings of the Great Lakes Symposium on VLSI 2022. 2022.
Firuzan, Arash, Mehdi Modarressi, and Midia Reshadi. "Reconfigurable network-on-chip based Convolutional Neural Network accelerator." Journal of Systems Architecture (2022): 102567.
Patil, Trupti, et al. "A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture." Wireless Communications and Mobile Computing 2022 (2022).
Khan, Kamil, Sudeep Pasricha, and Ryan Gary Kim. "RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers." Proceedings of the Great Lakes Symposium on VLSI 2022. 2022.
Salehnamadi, M. O. H. A. M. M. A. D. R. E. Z. A. "A Novel 3D Mesh-Based NoC Architecture for Performance Improvement." Majlesi Journal of Electrical Engineering 16.2 (2022).
Bhaskar, Adusumilli Vijaya. "A Detailed Power Analysis of Network-on-Chip." 2022 IEEE Delhi Section Conference (DELCON). IEEE, 2022.
Bhaskar, Adusumilli Vijaya. "Estimation of Power Consumption in a Network-on-Chip Router." 2022 IEEE Delhi Section Conference (DELCON). IEEE, 2022.
Singh, Sangeeta, J. V. R. Ravindra, and B. Rajendra Naik. "Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip." Transactions on Emerging Telecommunications Technologies (2022): e4514.
Downloads
Published
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.
All papers should be submitted electronically. All submitted manuscripts must be original work that is not under submission at another journal or under consideration for publication in another form, such as a monograph or chapter of a book. Authors of submitted papers are obligated not to submit their paper for publication elsewhere until an editorial decision is rendered on their submission. Further, authors of accepted papers are prohibited from publishing the results in other publications that appear before the paper is published in the Journal unless they receive approval for doing so from the Editor-In-Chief.
IJISAE open access articles are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License. This license lets the audience to give appropriate credit, provide a link to the license, and indicate if changes were made and if they remix, transform, or build upon the material, they must distribute contributions under the same license as the original.
