Noise Immune Schmitt Trigger Logic Gate Based Disturb Free Scalable 9T SRAM In Memory Computing Design
Keywords:
Static random-access memories, In-memory computing (IMC), Schmitt trigger, static noise margin and Ripple carry adder and multiplication.Abstract
In Von Neumann’s architecture, memory serves as a storage component, whereas the arithmetic logic unit (ALU) serves as a computation device. However, when a lot of data flows between the memory and the ALU, Von Neumann bottlenecks remain a serious problem, resulting in limitations related to temporal overhead, throughput, and energy efficiency. This paper develops an In-memory computing (IMC) structure for computing ripple carry addition and multiplication (RCA-M) processes directly in the memory array. Here, Half-Select Disturb-Free Write Assist (HDFWA) Static random-access memories (SRAM) cell is designed with 9 transistors to optimize the read and write static noise margin (SNM) individually. The current compensation based sensor circuit is used to reduce leakage power and improve reading performance. In addition, the control circuits of the proposed IMC architecture, including SRAM control, IMC control, and RCA-M, are designed using Schmitt trigger (ST) logic to enable noise-immune, reliable, and efficient IMC systems. By using the ST logic, switching power is greatly reduced, and noise immunity is increased. The simulation outputs demonstrate that the suggested IMC for RCA-M outperforms other IMC architectures in terms of average energy efficiency (4.019 fJ) on CMOS 14nm technology.
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Mittal, Sparsh, Gaurav Verma, Brajesh Kaushik, and Farooq A. Khanday. “A survey of SRAM-based in-memory computing techniques and applications.” Journal of Systems Architecture 119 (2021): 102276.
Gupta, Aman Kumar, and Abhishek Acharya. “Exploration of 9T SRAM cell for in memory computing application.” In 2021 Devices for Integrated Circuit (DevIC), pp. 461-465. IEEE, 2021.
Jhang, Chuan-Jia, Cheng-Xin Xue, Je-Min Hung, Fu-Chun Chang, and Meng-Fan Chang. “Challenges and trends of SRAM-based computing-in-memory for AI edge devices.” IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 5 (2021): 1773-1786.
Huo, Qiang, Yiming Yang, Yiming Wang, Dengyun Lei, Xiangqu Fu, Qirui Ren, Xiaoxin Xu et al. “A computing-in-memory macro based on three-dimensional resistive random-access memory.” Nature Electronics 5, no. 7 (2022): 469-477.
Xie, Shanshan, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, and Jaydeep P. Kulkarni. “eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters.” IEEE Journal of Solid-State Circuits (2023).
Jing, Zhaokun, Bonan Yan, Yuchao Yang, and Ru Huang. “VSDCA: A voltage sensing differential column architecture based on 1T2R RRAM array for computing-in-memory accelerators.” IEEE Transactions on Circuits and Systems I: Regular Papers 69, no. 10 (2022): 4028-4041.
Pham, Thi-Nhan, Quang-Kien Trinh, Ik-Joon Chang, and Massimo Alioto. “STT-BNN: A novel STT-MRAM in-memory computing macro for binary neural networks.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12, no. 2 (2022): 569-579.
Lin, Zhiting, Zhongzhen Tong, Jin Zhang, Fangming Wang, Tian Xu, Yue Zhao, Xiulong Wu et al. “A review on SRAM-based computing in-memory: Circuits, functions, and applications.” Journal of Semiconductors 43, no. 3 (2022): 031401.
Wang, Chua-Chin, and Chien-Ping Kuo. “67.5-fJ per access 1-kb SRAM using 40-nm logic CMOS process.” In 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4. IEEE, 2021.
K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, “A bitline leakage compensation scheme for low-voltage SRAMs,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 726–734, May 2001.
D. Kim, G. Chen, M. Fojtik, M. Seok, D. Blaauw, and D. Sylvester, “A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Rio de Janeiro, Brazil, May 2011, pp. 69–72.
A.-T. Do, Z.-H. Kong, K.-S. Yeo, and J. Y. S. Low, “Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 2, pp. 196–204, Feb. 2011.
M. S. M. Siddiqui, Z. C. Lee, and T. T.-H. Kim, “A 16-kb 9T ultralow-voltage SRAM with column-based split cell-VSS, data-aware write-assist, and enhanced read sensing margin in 28-nm FDSOI,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 29, no. 10, pp. 1707–1719, Oct. 2021.
Dhakad, Narendra Singh, Eshika Chittora, Gopal Raut, Vishal Sharma, and Santosh Kumar Vishvakarma. “In-Memory Computing with 6T SRAM for Multi-operator Logic Design.” Circuits, Systems, and Signal Processing (2023): 1-15.
Su, Jian-Wei, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu et al. “Two-way transpose multi-bit 6T SRAM computing-in-memory macro for inference-training AI edge chips.” IEEE Journal of Solid-State Circuits 57, no. 2 (2021): 609-624.
Song, Jiahao, Yuan Wang, Xiyuan Tang, Runsheng Wang, and Ru Huang. “A 16Kb transpose 6T SRAM in-memory-computing macro based on robust charge-domain computing.” In 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 1-3. IEEE, 2021.
Ammoura, Lila, Marie-Lise Flottes, Patrick Girard, and Arnaud Virazel. “Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures.” In 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 1-4. IEEE, 2021.
Saragada, Prasanna Kumar, Subashish Manna, Amandeep Singh, and Bishnu Prasad Das. “A Configurable 10 T SRAM-Based IMC Accelerator With Scaled-Voltage-Based Pulse Count Modulation for MAC and High-Throughput XAC.” IEEE Transactions on Nanotechnology (2023).
Zhang, Jin, Zhiting Lin, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, and Junning Chen. “An 8T SRAM array with configurable word lines for in-memory computing operation.” Electronics 10, no. 3 (2021): 300.
Rajput, Anil Kumar, Manisha Pattanaik, and Gaurav Kaushal. “Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture.” Microelectronics Journal 129 (2022): 105569.
Rajput, Anil Kumar, and Manisha Pattanaik. “Implementation of Boolean and arithmetic functions with 8T SRAM cell for in-memory computation.” In 2020 International Conference for Emerging Technology (INCET), pp. 1-5. IEEE, 2020.
Si, Xin, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu et al. “A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips.” IEEE Journal of Solid-State Circuits 56, no. 9 (2021): 2817-2831.
Mori, Haruki, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto. “A 28-nm FD-SOI 8T dual-port SRAM for low-energy image processor with selective sourceline drive scheme.” IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 4 (2018): 1442-1453.
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