Simulation and Analysis of Non-Inverting and Inverting Mixed Logic 2-4 Decoder
Keywords:
2:4 Decoder, Modified Mixed Logic Design(MMLD), Gate Diffusion Input(GDI), Dual Value Logic, 45nm TechnologyAbstract
This project involves analysis of Modified Mixed Logic Design abbreviated as MMLD which includes following design logics: Complementary Metal Oxide Semiconductor abbreviated to CMOS logic design, Gate Diffusion Input abbreviated as GDI technique, and Dual Value Logic called as DVL. Two logic styles are used in this paper to reduce power dissipation and delay time are fourteen transistor and fifteen transistor decoders. Every situation requires the use of both regular and inverted decoders. In comparison to conventional CMOS logic design, the suggested decoder provides full swing with a smaller number of transistor count. This suggested MMLD decoder is implemented at multiple frequencies with varied supply voltages using Pyxis Mentor Graphics tool at 45nm with PMOS of width (Wp)=1.4u & length (Lp)=0.35u, NMOS of width (Wn)=1.4u & length (Ln)=0.35u, Fan-out=1, and Wp/Wn=1, which exhibits a reduced power dissipation and delay when compared to other conventional logic design styles.
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