Design and Performance Analysis of FDOR with Label Switching Buffered and Bufferless Noc for Intelligent Low Power Communication Systems
Keywords:FDOR, Dynamic reconfiguration NoC along with FDOR (Dr-FDOR-NoC) Label switching algorithm, Buffered & Bufferless NoC TED-based Power reduction.
The existing network systems used to communicate on-chip networks have buffers to share and store packets to avoid contention and for memory optimization. To address these two issues, the deflection-based bufferless routing algorithms have been proposed recently as an alternative design for the current system, but power and area utilizations are more. A better solution for optimizing buffer-less routing systems has been presented in this work, and it guarantees power and area optimization with high throughput. When comparing these algorithms to the realistic design, the buffer less gave a significantly reduced performance. The proposed FDOR and Label switching (LS) are two different network topologies for routing and switching, effectively controlling the packet and successfully delivery of a packet, this lead to a high packet delivery ratio. While implementing the buffer-less algorithm, it is to be significantly less complex, and a comparison is made on the frequency, area, performance, and power conservations to the buffered counterparts. The flexible direction order routing algorithm (FDOR) inherits the advantages like deadlock, freedom, and simplicity, which uses a logic-based implementation of flexible direction order routing. The Dynamic reconfiguration NoC and FDOR have been designed and synthesized in the Xilinx software tool and implemented on Artix-7 FGPA. The proposed NoC has an 8x8 design with 64 routers incorporated with power reduction techniques before transmitting and after receiving packets. Based on synthesis results obtained with a buffer, less routing can lead to a reduction in the area by 27%., the power consumption is reduced by 31%, and the router cycle time is also reduced by 11%. Finally, FDOR with LS is tested and validated for streaming data transmission on FPGA under higher throughput and injection rate.
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