Design and Performance Analysis of FDOR with Label Switching Buffered and Bufferless Noc for Intelligent Low Power Communication Systems


  • Sujata S. B, Research Scholar, Department of Electronics and Communication, GNDEC, Bidar, VTU Belgaum Karnataka
  • Anuradha M. Sandi Professor, Department of Electronics and Communication, GNDEC, Bidar Karnataka


FDOR, Dynamic reconfiguration NoC along with FDOR (Dr-FDOR-NoC) Label switching algorithm, Buffered & Bufferless NoC TED-based Power reduction.


The existing network systems used to communicate on-chip networks have buffers to share and store packets to avoid contention and for memory optimization. To address these two issues, the deflection-based bufferless routing algorithms have been proposed recently as an alternative design for the current system, but power and area utilizations are more. A better solution for optimizing buffer-less routing systems has been presented in this work, and it guarantees power and area optimization with high throughput. When comparing these algorithms to the realistic design, the buffer less gave a significantly reduced performance. The proposed FDOR and Label switching (LS) are two different network topologies for routing and switching, effectively controlling the packet and successfully delivery of a packet, this lead to a high packet delivery ratio. While implementing the buffer-less algorithm, it is to be significantly less complex, and a comparison is made on the frequency, area, performance, and power conservations to the buffered counterparts. The flexible direction order routing algorithm (FDOR) inherits the advantages like deadlock, freedom, and simplicity, which uses a logic-based implementation of flexible direction order routing. The Dynamic reconfiguration NoC and FDOR have been designed and synthesized in the Xilinx software tool and implemented on Artix-7 FGPA. The proposed NoC has an 8x8 design with 64 routers incorporated with power reduction techniques before transmitting and after receiving packets. Based on synthesis results obtained with a buffer, less routing can lead to a reduction in the area by 27%., the power consumption is reduced by 31%, and the router cycle time is also reduced by 11%. Finally, FDOR with LS is tested and validated for streaming data transmission on FPGA under higher throughput and injection rate.


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C. Fallin et al., MinBD: minimally-buffered deflection routing for energy-efficient interconnect, in NOCS-4, Copenhagen, 2012.

Mandal S.K., Krishnakumar A., Ogres U.Y. (2021) Energy-Efficient Networks-on-Chip Architectures: Design and Run-Time Optimization. In: Mishra P., Charles S. (eds) Network-on-Chip Security and Privacy. Springer, Cham.

Tariq, U.U., Ali, H., Liu, L. et al. Energy-efficient scheduling of streaming applications in VFI-NoC-HMPSoC based edge devices. J Ambient Intell Human Comput 12, 9991–10007 (2021).

Subodh Charles, Yangdi Lyu, and Prabhat Mishra. 2019. Real-time detection and localization of DoS attacks in NoC-based SoCs. In Design, Automation & Test in Europe Conference & Exhibition. IEEE, 1160—1165.

Trupti Patil, Anuradha Sandi, Design and implementation of asynchronous NOC architecture with the buffer-less router, Materials Today: Proceedings, Volume 49, Part 3,2022, Pages 756-763, ISSN 2214-7853,

S.B., Sujata. and M. Sandi, A. (2021), "Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA", International Journal of Pervasive Computing and Communications, Vol. ahead-of-print No. ahead-of-print.

Yu Cai., "Comparative Evaluation of FPGA and ASIC Implementations of Bufferless and Buffered Routing Algorithms for On-Chip Networks ", 16th Int'l Symposium on Quality Electronic Design, 978-1-4799-7581-5/15,2015 IEEE.

MONIKA, "SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router", September 20, VOLUME 9, 2021, 2021, DOI 10.1109/ACCESS.2021.3111294

Juan Fang, Sitong Liu, Shijian Liu, Yanjin Cheng, Lu Yu, "Hybrid Network-on-Chip: An Application-Aware Framework for Big Data", Complexity, vol. 2018, Article ID 1040869, 11 pages, 2018.

Basavaraj Talwar. "Traffic engineered NoC for streaming applications", 0141-9331, 2013 Elsevier B.V., Microprocessors and Microsystems

Karthikeyan, A., Kumar, P.S. GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC. Cluster Comput 21, 177–187 (2018)., "Design and implementation of asynchronous NOC architecture with buffer-less router",, Materials Today: Proceedings

Karthikeyan, A., Kumar, P.S. GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC. Cluster Comput 21, 177–187 (2018).

C. Effiong, G. Sassatelli, and A. Gamatie, "Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing," 2017 Euromicro Conference on Digital System Design (DSD), 2017, pp. 171-178, DOI: 10.1109/DSD.2017.55

G. Nychis et al., On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-core Interconnects. SIGCOMM, 2012.

C. Bobda and A. Ahmadinia, “Dynamic interconnection of reconfigurable modules on reconfigurable devices,” Design Test of Computers, IEEE, vol. 22, no. 5, pp. 443–451, Sept 2005.

E. Wachter and F. Moraes, “Mazenoc: Novel approach for fault-tolerant NoC routing,” in SOC Conference (SOCC), 2012 IEEE International, Sept 2012, pp. 364–369.

A Strano, D. Bertozzi, F. Trivino, J. Sanchez, F. Alfaro, and J. Flich, “Osr-lite: Fast and deadlock-free NoC reconfiguration framework,” in Embedded Computer Systems (SAMOS), 2012 International Conference on, July 2012, pp. 86–95.

Gomez-Rodriguez, J.R.; Sandoval-Arechiga, R.; Ibarra-Delgado, S.; RodriguezAbdala, V.I.; Vazquez-Avila, J.L.; Parra-Michel, R. A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities. Micromachines 2021, 12, 183. mi12020183.

H. Chen, P. Chen, J. Zhou, L. H. K. Duong, and W. Liu, "ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2021.3091961

V. Venkataramani, B. Bodin, A. K. Mohite, T. Mitra and L. -S. Peh, "ASCENT: Communication Scheduling for SDF on Bufferless Software-defined NoC," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2021.3128445.

R. Mercier, C. Killian, A. Kritikakou, Y. Helen and D. Chillet, "BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021 DOI: 10.1109/TCAD.2021.3101406.

A. Das, A. Kumar, J. Jose, and M. Palesi, "Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty," in IEEE Transactions on Computers, vol. 70, no. 6, pp. 892-905, 1 June 2021, DOI: 10.1109/TC.2021.3069968.

B. Bhowmik, P. Hazarika, P. Kale, and S. Jain, "AI Technology for NoC Performance Evaluation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 12, pp. 3483-3487, Dec. 2021, DOI: 10.1109/TCSII.2021.3124297.

Sivaganesan, D. "Improvisation of a mesh network with wideband code division multiple access." Journal: IRO Journal on Sustainable Wireless Systems 3 (2019): 198-205.

Kiran, W. S., S. Smys, and V. Bindhu. "Clustering of WSN Based on PSO with Fault Tolerance and Efficient Multidirectional Routing." Wireless Personal Communications 121, no. 1 (2021): 31-47.

Ashokkumar, N., P. Nagarajan, and P. Venkatramana. "3D (dimensional)—Wired and wireless network-on-chip (NoC)." In Inventive Communication and Computational Technologies, pp. 113-119. Springer, Singapore, 2020.

Gangula, R. ., Vutukuru, M. M. ., & Kumar M., R. . (2023). Network Intrusion Detection Method Using Stacked BILSTM Elastic Regression Classifier with Aquila Optimizer Algorithm for Internet of Things (IoT). International Journal on Recent and Innovation Trends in Computing and Communication, 11(2s), 118–131.

Prof. Madhuri Zambre. (2016). Analysis and Modeling of Physical Stratum for Power Line Communication. International Journal of New Practices in Management and Engineering, 5(01), 08 - 13. Retrieved from

Nagendram, S., Singh, A., Harish Babu, G., Joshi, R., Pande, S.D., Ahammad, S.K.H., Dhabliya, D., Bisht, A. Stochastic gradient descent optimisation for convolutional neural network for medical image segmentation (2023) Open Life Sciences, 18 (1), art. no. 20220665, .




How to Cite

S. B, , S. ., & Sandi, A. M. . (2023). Design and Performance Analysis of FDOR with Label Switching Buffered and Bufferless Noc for Intelligent Low Power Communication Systems. International Journal of Intelligent Systems and Applications in Engineering, 12(4s), 375–387. Retrieved from



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