Enhancing Chip Design Performance with Machine Learning and PyRTL

Authors

  • Isra Aljrah The Department of Mathematics and Statistics Jordan University of Science and Technology
  • Ghaith Alomari The Department of Mathematics and Computer Science, Chicago State University
  • Maymoona Aljarrah The Department of Mathematical Sciences, university kebangsaan Malaysia
  • Anas Aljarah The Department of Mathematical Sciences, university kebangsaan Malaysia
  • Bilal Aljarah The Department of Electrical Power Engineering ,Yarmouk university

Keywords:

Chip, digital, facilities, hardware, machine learning, python, techniques

Abstract

The contemporary world of digital design is evolving rapidly, and the tools at our disposal are expanding in tandem. This paper presents a comprehensive methodology for designing a chip using PyRTL, a Python-based hardware description language. Beginning with the basics of setting up the environment, the paper walks through designing an adder circuit, complete with memory integration, all the way through to simulation. Furthermore, we integrate modern data analytics by utilizing machine learning (ML) techniques to assess performance metrics, offering a holistic approach to chip design. Machine learning models predict key performance indicators like latency, power consumption, and efficiency, based on simulation data. The results serve as a foundation for iterative design improvements, ensuring the chip's robustness in real-world applications. This integration of traditional design techniques with cutting-edge data analysis illuminates the future of chip design, showcasing the potential of ML in electronic design automation.

Downloads

Download data is not yet available.

References

Huang, G., Hu, J., He, Y., Liu, J., Ma, M., Shen, Z., Wu, J., Xu, Y., Zhang, H., Zhong, K. and Ning, X., 2021. Machine learning for electronic design automation: A survey. ACM Transactions on Design Automation of Electronic Systems (TODAES), 26(5), pp.1-46..

A. Arunkumar, E. Bolotin, B. Cho, U. Milic, E. Ebrahimi, O. Villa, A. Jaleel, C.-J. Wu, D. Nellans, Mcm-gpu: Multi-chip-module gpus for continued performance scalability, in: 2017 ACM/IEEE [209] T.-C. Chen, P.-Y. Lee, T.-C. Chen, Automatic floorplanning for ai socs, in: 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2020, pp. 1–2. doi:10.1109/ 44th Annual International Symposium on Computer Architecture VLSI-DAT49148.2020.9196464. (ISCA), 2017, pp. 320–332. doi:10.1145/3079856.3080231.

C. K. C. Lee, Deep learning creativity in eda, in: 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2020, pp. 1–1.

T.-W. Chen, C.-S. Tang, S.-F. Tsai, C.-H. Tsai, S.-Y. Chien, L.-G. Chen, Tera-scale performance machine learning soc (mlsoc) with dual stream processor architecture for multimedia content analysis, IEEE Journal of Solid-State Circuits 45 (2010) 2321–2329. L. Wang, M. Luo, Machine learning applications and opportunities in ic design flow, in: 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2019, pp. 1–3.

M. Belleville, O. Thomas, A. Valentian, F. Clermidy, Designing digital circuits with nano-scale devices: Challenges and opportunities, Solid-State Electronics 84 (2013) 38–45. Selected Papers from the ESSDERC 2012 Conference

A. R. Brown, N. Daval, K. K. Bourdelle, B. Nguyen, A. Asenov, Comparative simulation analysis of process-induced variability in nanoscale soi and bulk trigate finfets, IEEE Transactions on Electron Devices 60 (2013) 3611–3617.

Yu-Hsin Chen, Tushar Krishna, Joel S Emer, and Vivienne Sze. 2016. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE Journal of Solid-State Circuits 52, 1 (2016), 127–138

David Koeplinger, Matthew Feldman, Raghu Prabhakar, Yaqi Zhang, Stefan Hadjis, Ruben Fiszel, Tian Zhao, Luigi Nardi, Ardavan Pedram, Christos Kozyrakis, et al. 2018. Spatial: A language and compiler for application accelerators. In Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation. ACM, 296–311.

John L. Hennessy and David A. Patterson. 2011. Computer Architecture, Fifth Edition: A Quantitative Approach (5th. ed.). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, ISBN:978-0-12-383872-8 https://dl.acm.org/doi/book/10.5555/1999263

J. Mahler, “MIPS CPU implemented in Verilog,” 2016. [Online]. Available: https://github.com/jmahler/mips-cpu

E. Lujan, “VHDL Implementation of a basic Pipeline MIPS processor,” 2016. [Online]. Available: https://opencores.org/project,vhdl-pipelinemips

J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Avizienis, ˇ J. Wawrzynek, and K. Asanovic, “Chisel: constructing hardware in a ´ scala embedded language,” in Proceedings of the 49th Annual Design Automation Conference. ACM, 2012, pp. 1216–1225.

Baaij, C.P., 2015. Digital circuit in CλaSH: functional specifications and type-directed synthesis.

J. Decaluwe, “Myhdl: a python-based hardware description language,” Linux journal, vol. 2004, no. 127, p. 5, 2004.

D. Lockhart, G. Zibrat, and C. Batten, “Pymtl: A unified framework for vertically integrated computer architecture research,” in 47th IEEE/ACM Int’l Symp. on Microarchitecture (MICRO), Dec 2014, pp. 280–292.

E. Logaras and E. S. Manolakos, “Syspy: using python for processorcentric soc design,” in Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. IEEE, 2010, pp. 762–765.

A. Mashtizadeh, “Phdl: A python hardware design framework,” Ph.D. dissertation, Massachusetts Institute of Technology, 2007

A. Pellegrini, K. Constantinides, D. Zhang, S. Sudhakar, V. Bertacco, and T. Austin, “Crashtest: A fast high-fidelity fpga-based resiliency analysis framework,” in Computer Design, 2008. ICCD 2008. IEEE International Conference on. IEEE, 2008, pp. 363–370.

S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, “A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor,” in Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 2003, p. 29.

Clow, J., Tzimpragos, G., Dangwal, D., Guo, S., McMahan, J. and Sherwood, T., 2017, September. A pythonic approach for rapid hardware prototyping and instrumentation. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1-7). IEEE.

Amuru, D., Zahra, A., Vudumula, H.V., Cherupally, P.K., Gurram, S.R., Ahmad, A. and Abbas, Z., 2023. AI/ML algorithms and applications in VLSI design and technology.

Ghaith,A.*,Anas,J.,2021. Efficiency of Using the Diffie-Hellman Key in Cryptography for Internet Security.

Talafha, M. ,Alkouri, A., Alqaraleh, S, Zureigat, H .,Aljarrah, A. Complex hesitant fuzzy sets and its applications in multiple attributes decision-making problems.

Razak ,S., Oqla m., Anas ,A., Abd ULazeez ,A. Complex Fuzzy Parameterized Soft Set.

Ahmed ,S., Anas ,A., Sek Sok, K., Zaidi ,I. Robust estimation and outlier detection on panel data: an application to environmental science.

Downloads

Published

25.12.2023

How to Cite

Aljrah, I. ., Alomari, G. ., Aljarrah, M. ., Aljarah, A. ., & Aljarah, B. . (2023). Enhancing Chip Design Performance with Machine Learning and PyRTL. International Journal of Intelligent Systems and Applications in Engineering, 12(2), 467–472. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/4291

Issue

Section

Research Article