Enhancing Chip Design Performance with Machine Learning and PyRTL


  • Isra Aljrah The Department of Mathematics and Statistics Jordan University of Science and Technology
  • Ghaith Alomari The Department of Mathematics and Computer Science, Chicago State University
  • Maymoona Aljarrah The Department of Mathematical Sciences, university kebangsaan Malaysia
  • Anas Aljarah The Department of Mathematical Sciences, university kebangsaan Malaysia
  • Bilal Aljarah The Department of Electrical Power Engineering ,Yarmouk university


Chip, digital, facilities, hardware, machine learning, python, techniques


The contemporary world of digital design is evolving rapidly, and the tools at our disposal are expanding in tandem. This paper presents a comprehensive methodology for designing a chip using PyRTL, a Python-based hardware description language. Beginning with the basics of setting up the environment, the paper walks through designing an adder circuit, complete with memory integration, all the way through to simulation. Furthermore, we integrate modern data analytics by utilizing machine learning (ML) techniques to assess performance metrics, offering a holistic approach to chip design. Machine learning models predict key performance indicators like latency, power consumption, and efficiency, based on simulation data. The results serve as a foundation for iterative design improvements, ensuring the chip's robustness in real-world applications. This integration of traditional design techniques with cutting-edge data analysis illuminates the future of chip design, showcasing the potential of ML in electronic design automation.


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How to Cite

Aljrah, I. ., Alomari, G. ., Aljarrah, M. ., Aljarah, A. ., & Aljarah, B. . (2023). Enhancing Chip Design Performance with Machine Learning and PyRTL. International Journal of Intelligent Systems and Applications in Engineering, 12(2), 467–472. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/4291



Research Article