Implementation of Enhanced Hardware Digital System Design by Protecting Hardware Trojans using Concurrent Error Detection Technique


  • S. Nithyadevi Assistant Professor Sri Krishna College of Technology, Coimbaatore-641042
  • S. Senthilkumar Assistant Professor Sri Krishna College of Engineering and Technology, Coimbatore-641008
  • Biji Rose Assistant Professor (SG), Department of Electronics and Communication Engineering, Dr. N. G. P Institute of Technology, Coimbatore
  • A. Vijayalakshmi Associate Professor Department of ECE, Hindustan College of engineering and technology, Coimbatore
  • T. Velmurugan Assistant Professor Department of ECE Builder engineering college, Kangayam
  • S. A. Sivakumar Associate Professor Department of Electronics and Communication Engineering Dr. N. G. P Institute of Technology, Coimbatore
  • Dharmesh Dhabliya Department of Information Technology Vishwakarma Institute of Information Technology, Pune, India 7


Concurrent Error Detection (CED) techniques, Code Division Multiple Access (CDMA), Hardware Trojan, System On Chip (SoC)


Malicious threat attacks of hardware design   which are caused by third parties during Integrated Circuit(IC) fabrication process has been considered as primary security issue. Due to this attack the malicious alteration is occurred in electronic hardware design which results in failure or loss of information.  This is called Hardware Trojan. To prevent the attacks during synthesis, a Concurrent Error Detection (CED) technique which is based on 128 bit encryption key generator derived from Code Division Multiple Access (CDMA) is proposed in this paper. This proposed technique is used to protect the Digital Systems from Hardware Trojan attacks and also faults can easily be detected.

The proposed technique can also be used for split-manufacturing methods in all digital circuits with minimum area overhead and less hardware complexity. The simulation results prove that the proposed method can be applicable for implementing the design in System On Chip (SoC).


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Rajit Karmakar, N. Prasad, Santanu Chattopaddhaya, Rohit Kumar and Indranil Sengupta “ A New Logic Encryption Strategy Ensuring Key Interdependency”. 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, 2017, pp. 429-434.

Nandeesha Veeranna and Benjamin Carrion Schafer “Hardware Trojan Avoidance and Detection for Dynamically Re-configuarable FPGAs” 2016 International Conference on Field Programmable Technology (FPT) Dec 2016, pp. 1-4.

Jiliang Zhang “A Practical Logic Obfuscation Technique for Hardware Security.” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 3, March 2016, pp. 1193-1197.

N. Fern, S. Kulkarni, and K. T. T. Cheng. “Hardware Trojans hidden in RTL don't cares Automated insertion and prevention methodologies". Test Conference (ITC), IEEE International, Dec.2015, pp. 1-8.

K. Xiao, D. Forte, and M. Tehranipoor, “A novel built-in self authentication technique to prevent inserting hardware Trojans,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 33, no. 12, Dec. 2014,pp. 1778–1791.

Swarup Bhunia, “Hardware Trojan Attacks: Threat Analysis and Countermeasures”. Proceedings of IEEE, vol.2, no.8, Aug 2014, pp. 1229-1247.

N. Nowroz, K. Hu, F. Koushanfar, and S. Reda, “Novel techniques for high-sensitivity hardware Trojan detection using thermal and power maps,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 33,no. 12, Dec. 2014 pp. 1792–1805.

Waksman, M. Suozzo, and S. Sethumadhavan, “FANCI: Identification of stealthy malicious logic using Boolean functional analysis,” Proceedings of the ACM Computer and Communications Security’13(CCS’13), Berlin, Germany, Nov. 2013, pp. 697–708.

Sheng Wei and Miodrag Potkonjak “Scalable Hardware Trojan Diagnosis” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 6, june 2012, pp. 1049-1057.

H. Salmani, M. Tehranipoor, and J. Plusquellic, “A novel technique for improving hardware Trojan detection and reducing Trojan activation time,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20,no. 1, Jan. 2012, pp. 112–125.

Huafeng Liu and Hongei Luo, LiweiWang “Design of Hardware Trojan Horse Based on Counter” International Conference on Quality, Reliability, Risk, Maintenance, and Safety Engineering, June 2011, pp. 1-3.

Baumgarten, A. Tyagi, and J. Zambreno, “Preventing IC piracy using reconfigurable logic barriers,” IEEE Des. Test Comput. vol. 27, no. 1, Jan./Feb. 2010 ,pp. 66–75.

M. Potkonjak, A. Nahapetian, M. Nelson, and T. Massey, “Hardware Trojan horse detection using gate-level characterization,” Proceedings of the 46th ACM/IEEE Design Automation’09 (DAC’09) conference, San Francisco, CA, USA, Jul. 2009, pp. 688–693.

M. Abramovici and P. Bradley, “Integrated circuit security: New threats and solutions,” Article No.55, Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research’09 (CSIIRW’09), Knoxville, TENNESSEE, USA, Apr.2009, pp. 1–3.

N. A. Touba and E. J. McCluskey, “Logic synthesis of multilevel circuits with concurrent error-detection,” IEEE Trans. Comput.-Aided DesignIntegr. Circuits Syst., vol. 16, no. 7, Jul. 1997, pp. 783–789.




How to Cite

Nithyadevi, S. ., Senthilkumar, S. ., Rose, B. ., Vijayalakshmi, A. ., Velmurugan, T. ., Sivakumar, S. A. ., & Dhabliya, D. . (2024). Implementation of Enhanced Hardware Digital System Design by Protecting Hardware Trojans using Concurrent Error Detection Technique. International Journal of Intelligent Systems and Applications in Engineering, 12(15s), 556–564. Retrieved from



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