Implementation of Enhanced Hardware Digital System Design by Protecting Hardware Trojans using Concurrent Error Detection Technique

Authors

  • S. Nithyadevi Assistant Professor Sri Krishna College of Technology, Coimbaatore-641042
  • S. Senthilkumar Assistant Professor Sri Krishna College of Engineering and Technology, Coimbatore-641008
  • Biji Rose Assistant Professor (SG), Department of Electronics and Communication Engineering, Dr. N. G. P Institute of Technology, Coimbatore
  • A. Vijayalakshmi Associate Professor Department of ECE, Hindustan College of engineering and technology, Coimbatore
  • T. Velmurugan Assistant Professor Department of ECE Builder engineering college, Kangayam
  • S. A. Sivakumar Associate Professor Department of Electronics and Communication Engineering Dr. N. G. P Institute of Technology, Coimbatore
  • Dharmesh Dhabliya Department of Information Technology Vishwakarma Institute of Information Technology, Pune, India 7

Keywords:

Concurrent Error Detection (CED) techniques, Code Division Multiple Access (CDMA), Hardware Trojan, System On Chip (SoC)

Abstract

Malicious threat attacks of hardware design   which are caused by third parties during Integrated Circuit(IC) fabrication process has been considered as primary security issue. Due to this attack the malicious alteration is occurred in electronic hardware design which results in failure or loss of information.  This is called Hardware Trojan. To prevent the attacks during synthesis, a Concurrent Error Detection (CED) technique which is based on 128 bit encryption key generator derived from Code Division Multiple Access (CDMA) is proposed in this paper. This proposed technique is used to protect the Digital Systems from Hardware Trojan attacks and also faults can easily be detected.

The proposed technique can also be used for split-manufacturing methods in all digital circuits with minimum area overhead and less hardware complexity. The simulation results prove that the proposed method can be applicable for implementing the design in System On Chip (SoC).

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References

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Published

07.02.2024

How to Cite

Nithyadevi, S. ., Senthilkumar, S. ., Rose, B. ., Vijayalakshmi, A. ., Velmurugan, T. ., Sivakumar, S. A. ., & Dhabliya, D. . (2024). Implementation of Enhanced Hardware Digital System Design by Protecting Hardware Trojans using Concurrent Error Detection Technique. International Journal of Intelligent Systems and Applications in Engineering, 12(15s), 556–564. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/4790

Issue

Vol. 12 No. 15s (2024)

Section

Research Article

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