End-to-End Machine Learning Pipeline for Chip Design, Verification, and Testing
Keywords:
Machine Learning, Pipeline, Chip Design, Verification, and TestingAbstract
The emergence of increased complexity in modern semiconductor systems has rendered the conventional Electronic Design Automation (EDA) flows ineffective because of their prolonged design configurations, labor intensive verification, and slow testing process. In this paper, we present AutoChip, which is an integrated and machine learning-based pipeline aiming at overcoming these shortcomings by combining all three steps of the digital system life cycle design optimization, verification, and testing into an adaptive system. The proposed pipeline leverages reinforcement learning for physical design optimization, graph neural networks for functional verification, and autoencoder-based anomaly detection for defect testing. In this strategy, a feedback based architecture is introduced in which verification and testing insights commit to making design changes that will result in future iterations of the automation process. Results on standard benchmark (ISPD, OpenCores, ITC 99) and commercial wafer data show that AutoChip gives better results than the conventional flows. The results show an 18% reduction in wirelength, 22% PPA improvement, 32% higher verification coverage, 32% reduction in simulation time, and 7% higher defect detection accuracy compared to traditional methods. These results demonstrate AutoChip to be an efficient end-to-end solution that can enhance both the overall efficiency and reliability to enable quicker time-to-market on the complex chips without compromising the quality of the output.
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