Design for Testability (DFT) Techniques in Modern VLSI Chips
Keywords:
Design for Testability, VLSI, Scan Chain, BIST, Fault Coverage.Abstract
Development of the DFT techniques has become an essential part of the present-day VLSI chip design due to the growing complexity, density, and performance demands of the integrated circuits. This paper comprises a result oriented work on the resources and success of diverse forms of DFT methods in contemporary semiconductor devices and their effect on fault coverage, test-taking time, and area overlay. All the methods and processes of scan chain insertion, built-in self-test (BIST), boundary scan, and test compression among others are studied and tested under practical VLSI design conditions. The paper presents how the effective integration of DFT can have a positive impact on testability and presents practical case studies and experimental results gathered on industry-level ASIC design flows to exemplify the work. The findings indicate that scan-based testing contributed to the enhancement of controllability and observability and as a result, the logic fault coverage was 98.5 percent. Additionally, memory modules with BIST were created, so on-speed testers did not require any external equipment. Compression techniques, including embedded deterministic test (EDT) efficiently cut the test data volume by more than 40 per cent resulting in the corresponding decrease of the test application time. The area trade-offs with the DFT methods were also compared and most DFT methods exhibited less than 5 percent area overhead with a significant increase in test coverage and further enhancement in diagnostic capabilities. It is this paper that concludes that well-planned DFT techniques are vital in making the production of VLSI reliable and cost effective. The findings not only affirm that DFT integration is not a mere design requirement but also a significant facilitator of high-quality silicon.
Downloads
References
W. Needham, "Microprocessor testing today," IEEE Design & Test of Computers, vol. 15, no. 3, pp. 56–57, Jul.–Sept. 1998.
M. P. Kusko, B. J. Robbins, T. J. Snethen, P. Song, T. G. Foote, and W. V. Huott, "Microprocessor test and test tool methodology for the 500MHz IBM S/390 G5 chip," in Proc. Int. Test Conf. (ITC '98), Washington DC, USA: IEEE CS Press, 1998, pp. 717–726.
M. Abadir and S. Dasgupta, "Microprocessor test and verification," IEEE Design & Test of Computers, vol. 17, no. 4, pp. 4–5, Oct.–Dec. 2000.
A. L. Crouch et al., "The test development for a third-version ColdFire microprocessors," IEEE Design & Test of Computers, vol. 17, no. 4, pp. 29–37, Oct.–Dec. 2000.
D. M. Wu et al., "An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor," in Proc. Int. Test Conf. (ITC '04), Charlotte, NC, USA: IEEE CS Press, 2004, pp. 38–47.]
P. J. Tan et al., "Testing of UltraSPARC T1 microprocessor and its challenges," in Proc. Int. Test Conf. (ITC '06), Santa Clara, CA, USA: IEEE CS Press, 2006, paper 16.1.
R. Molyneaux et al., "Design-for-testability features of the Sun Microsystems Niagara2 CMP/CMT SPARC chip," in Proc. Int. Test Conf. (ITC '07), Santa Clara, CA, USA: IEEE CS Press, 2007, paper 1.2.
A. Sehgal et al., "Test cost reduction for the AMD Athlon processor using test partitioning," in Proc. Int. Test Conf. (ITC '07), Santa Clara, CA, USA: IEEE CS Press, 2007, paper 1.3.
X. Lin et al., "High-frequency, at-speed scan testing," IEEE Design & Test of Computers, vol. 20, no. 5, pp. 17–25, Sept.–Oct. 2003.
Z. Li et al., "Microarchitecture and performance analysis of Godson-2 SMT processor," in Proc. Int. Conf. Computer Design (ICCD '06), San Jose, CA, USA: IEEE CS Press, 2006, pp. 485–490.
W. Hu et al., "Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology," Journal of Computing Science and Technology, vol. 22, no. 1, pp. 1–14, Jan. 2007.
D. Wang et al., "The design-for-testability features of a general purpose microprocessor," in Proc. Int. Test Conf. (ITC '07), Santa Clara, CA, USA: IEEE CS Press, 2007, paper 9.2.
B. Cory et al., "Speed binning with path delay test in 150-nm technology," IEEE Design & Test of Computers, vol. 20, no. 5, pp. 41–45, Sept.–Oct. 2003.
X. Fan et al., "A solution for at-speed test based on internal PLL," Journal of Computer-Aided Design & Computer Graphics, vol. 19, no. 3, pp. 366–370, Mar. 2007. (In Chinese)
H. Furukawa, X. Wen, L. T. Wang, B. Sheu, Z. Jiang, and S. Wu, "A novel and practical control scheme for inter-clock at-speed testing," in Proc. Int. Test Conf. (ITC '06), Santa Clara, CA, USA: IEEE CS Press, 2006, paper 17.2.
K. Hatayama, M. Nakao, and Y. Sato, "At-speed built-in test for logic circuits with multiple clocks," in Proc. Asia Test Symp., Guam, USA, 2002, pp. 18–20.
X. Fan et al., "An on-chip test clock control scheme for multi-clock at-speed testing," in Proc. Asia Test Symp. (ATS '07), Beijing, China: IEEE CS Press, 2007, pp. 341–348.
Downloads
Published
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.
All papers should be submitted electronically. All submitted manuscripts must be original work that is not under submission at another journal or under consideration for publication in another form, such as a monograph or chapter of a book. Authors of submitted papers are obligated not to submit their paper for publication elsewhere until an editorial decision is rendered on their submission. Further, authors of accepted papers are prohibited from publishing the results in other publications that appear before the paper is published in the Journal unless they receive approval for doing so from the Editor-In-Chief.
IJISAE open access articles are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License. This license lets the audience to give appropriate credit, provide a link to the license, and indicate if changes were made and if they remix, transform, or build upon the material, they must distribute contributions under the same license as the original.
