Challenges And Solutions in Post-Manufacturing Testing of System-On-Chip (SOC) Devices
Keywords:
System-on-Chip (SoC), Post-Manufacturing Testing, Fault Coverage, Scan Compression, Built-In Self-Test (BIST)Abstract
The testing of System-on-Chip (SoC) devices after-manufacture is extremely pertinent to quality assurance of existence, credibility, and yield of sophisticated semiconductor manufacturing. Due to this ongoing increase in SoC complexity (high core counts, embedded IPs, high speed interfaces) the challenges of high fault coverage, fast test execution and low power effects have become more pronounced. This study demonstrates an experimental and theoretical study of the testing methods that are required to cater to these changing needs. The strategy that was formulated entailed the deterministic test vectors, scan compression methodology, at-speed Built-In Self-Test (BIST), and intelligent data analysis technique in order to analyze limitations posed by the fault detection schemes, the test time, and the power consumption. The findings pointed to fault coverage gaining proportional improvement as test vectors increased but with diminishing returns above a certain point and the eventual necessity of optimized sets of vectors. Scan compression significantly decreased test time, but it resulted in an increased power consumption showing that there is a trade-off between the effects of scan compression and scan compression power consumption which has to be traded off stringently in the design-for-test strategies. The paper has also provided variation in the extent of fault-type detection in that delay faults are more elusive than stuck-at or bridging fault detection and consequently, illustrates the relevance of hybrid testing methods. Moreover, advanced analytics of data allowed recognizing of marginal devices and forecast of failures and converted test results into meaningful process enhancement and reliability prediction. These results endorse a change toward adaptive, data-driven ways of testing that unite structural economy and predictive power. The framework proposed will provide intelligent and expandable solution to testing requirement of modern SoC product with the improved product quality and high manufacturing yield.
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