An Intelligent 64-bit parallel CRC for high-speed communication system applications

Authors

  • Ajay Sudhir Bale Dept. of ECE, New Horizon College of Engineering, Bengaluru, India
  • Karmanyaraj Singh Yadav Viterbi School of Engineering , (Electrical and Computer Engineering ), University of Southern California ( USC ) , California
  • Mahboob Alam Manav Rachna International Institute of Research and Studies Faridabad
  • Abhinav Shrivastava Assistant Professor, Symbiosis Law School (SLS), Symbiosis International (Deemed University) (SIU), Vimannagar, Pune, Maharashtra, India
  • Raj A. Varma Assistant Professor, Symbiosis Law School (SLS), Symbiosis International (Deemed University) (SIU), Vimannagar, Pune, Maharashtra, India
  • Rajdeep Singh Solanki Assistant professor, Medi-caps university indore, Computer science department,
  • Mamta B. Savadatti Dept. of ECE, New Horizon College of Engineering, Bengaluru, India

Keywords:

Redundancy check, Error control coding, Shift register, Parallel CRC calculation

Abstract

In the networking context, CRC plays a critical function in detecting mistakes. It is essential to improve the pace of CRC creation in order to keep up with the speed of data transmission. The cyclic redundancy check is well-known among engineers (CRC). Many people are becoming aware that it is used to identify bit mistakes in communication channels and that it is fundamentally a residual of the modulo-2-long division operation. These linear feedback shift registers (LFSRs), which process data serially, often are used in the hardware implementation of CRC calculations as a crucial technique for dealing with data mistakes. This CRC code’s serial computation cannot reach a high throughput. The throughput of CRC computations may be substantially increased by using constant concurrent CRC calculations. The CRC-16BISYNC protocol, CRC32 for error detection in Ethernet; CRC8 for ATM; CRC-CCITT for the X-25 set of rules, disc storage, XMODEM, and SDLC are all examples of applications that utilize CRCs of various types. We have focused on the main features and the trends of 64bit parallel CRC architecture and applications.

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Published

16.08.2023

How to Cite

Bale, A. S. ., Yadav, K. S. ., Alam, M. ., Shrivastava, A. ., Varma, R. A. ., Solanki, R. S. ., & Savadatti, M. B. . (2023). An Intelligent 64-bit parallel CRC for high-speed communication system applications. International Journal of Intelligent Systems and Applications in Engineering, 11(10s), 543–551. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/3310

Issue

Vol. 11 No. 10s (2023)

Section

Research Article

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